dummy core between two VIP using SOPC builder

[Altera_Forum]

Hi all 

I am working on a simple Verilog block that should interface with avalon-ST and avalon-ST protocol. right now, the code I've written for sopc builder is this    --- Quote Start ---   module dummy_block(   din_endofpacket,   din_startofpacket,   clock,   dout_ready,   din_valid,   din_data,   dout_endofpacket,   dout_startofpacket,   din_ready,   dout_valid,   dout_data  );    //the sink  input clock;  input din_endofpacket;  input din_startofpacket;  output dout_ready;  input din_valid;  input [15:0] din_data;    //the source  output dout_endofpacket;  output dout_startofpacket;  input din_ready;  output dout_valid;  output [15:0] dout_data;    wire reset;    reg [7:0] data_y;  reg [7:0] data_c;  reg din_endofpacket_i,din_startofpacket_i,din_valid_i,din_ready_i,dout_valid_i;    assign dout_ready = din_ready_i;  assign dout_endofpacket = din_endofpacket_i;  assign dout_startofpacket = din_startofpacket_i;  assign dout_valid = din_valid_i;  assign dout_data[15:0]={data_y,data_c};    assign reset=1'b0;    always@(posedge clock or posedge reset)  begin   if (reset) begin   data_y<=8'b0;   data_c<=8'b0;     din_endofpacket_i<=1'b0;   din_startofpacket_i<=1'b0;   din_valid_i<=1'b0;   din_ready_i<=1'b0;   end   else begin     data_y<=din_data[15:8];   data_c<=din_data[7:0];     din_endofpacket_i<=din_endofpacket;   din_startofpacket_i<=din_startofpacket;   din_valid_i<=din_valid;   din_ready_i<=din_ready;     end   end  endmodule  --- Quote End ---  I WANT to use registers, becouse next I'll have to work on video pakets. If i use only simple assignments it works fine. If I use registers, the system does not work at all. Input and output signal are correctly interfaced with related signals on avalon-ST (i don't know how to post the sopc block here..) could anyone help me please? best regards Phate  resolved inserting streaming adapters and setting latency for streaming sink and source to 3.

[Altera_Forum]

Have you resolved this without using the latency of 3?

[Altera_Forum]

Hi 

no, I didn't, but for my application is not a big problem a latency of 3 clock cycles.. using "assign" instead of registers, the block does not need latencyes (is like a wired connection...) beste regards  Phate

[Altera_Forum]

Ok, thanks. I was asking because I run into the exact same thing.. assigns go through no problem but registered wouldn't...  

 I'm trying to understand why these adapters would be required in a simple pass-through logic though. The timing relationships shouldn't change inside the block at all and all control packets should go through without issues too as long as the 4 lsbs are kept intact.. still learning.

[Altera_Forum]

I suppose (but I'm not sure) that it's due to the readwrite latency transfer. 

looking at the avalon spec, the ready latency shows when data wil be read(or write) to that sink. when a block asserts din ready, the previous is set to assert datavalid andoter signals one clock cicle later (ready latency=1, so the next clock cicle) Using registered ports adds at least two clock cycles latency (one cycle to read and one to write), so when te previous block in the data path will receive the din ready, next block won't be in a din ready state. Hope i am not wrong and that I'd been clear enough! best regards phate.

[Altera_Forum]

Hi phate, 

 Did you succeed to obtain video packets?

[Altera_Forum]

Hi 

yes, essentially after the SOP condition, every packet is sent ad data_valid high signal (as from the vip datasheet). So when i get a valid video packet I can process that packet.

[Altera_Forum]

phate actually I freeze the video and want to take that image from ddr which is fed by the frame buffer.But it is said in the VIP suite user manual that in ddr also exists non image packets(control packets).So I need to get rid of the control packets from that stream and I do not know how to implement an ip which does this job. Can you share your dummy core with me may be by looking at that I can found out how can I implement this ip as a custom component in SOPC.

[Altera_Forum]

its pretty straight forward to build a core that only passes on the video data not the control packets. at every SOP and VALID, check the DATA least significant nibble for control or data. if the type is data then pass on the following DATA packets when VALID is asserted until EOP (or a new SOP). i did something similar in my packet decoder: 

 http://www.alterawiki.com/wiki/vip_control_decoder  i'm not sure what you're going to do with the data to get it to your PC

[Altera_Forum]

I want to send freezed image to another computer.

[Altera_Forum]

I made a similar decoder time ago in verilog, it seems to work. 

Here it is, if you still need it.  module vip_decoder ( input wire clock, // clock.clk  input wire reset, // .reset   // sinkA  input din0_endofpacket, input din0_startofpacket, input din_ready, input din0_valid, input [15:0] din0_data,   output enable );   reg go = 1'b0; reg [4:0] check_sop; reg din_ready_i, din0_endofpacket_i, din0_startofpacket_i, din0_valid_i;   always@(posedge clock)begin   if (go==0) begin  if (din0_startofpacket) begin   check_sop = din0_data[4:0];  if((check_sop==4'b0)&(din0_valid)) go=1'b1;   end  end//end if go == 0  else if (go==1'b1)   begin  if (din0_endofpacket) go = 1'b0;  end end//end always@posedge clock  assign enable = go; endmodule  N.B. I know it coul be mde better , but for my sake, it worked!. Best regards Phate. p.s. this is a modified versione, the original one i made had both the sink and the source and all the others signals. Right now, I can't find the other bloks I wrote. I didn't work on FPGA for three or foru months, so I have to find them.