FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5987 Discussions

output source synchronic clk using altlvds

Altera_Forum
Honored Contributor II
767 Views

I want to use altlvds like this: 

use 4:1 altlvds output serial data,in order to output source synchronic clk,i use anothers 4:1 altlvds to sample input clk,Is this a right way?I know that the clk route throught global clk network,if I use clk as a signal ,it will be routed throught logic,will the performance be slower?
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
74 Views

The serializer that sends out the clock shouldn't be sampling the clock. Just tie off the 4 inputs to 1010 and you will send out a clock alongside your data. That should very nicely match your data output and you should have good timing.

Reply