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Altera_Forum
Honored Contributor I
725 Views

output source synchronic clk using altlvds

I want to use altlvds like this: 

use 4:1 altlvds output serial data,in order to output source synchronic clk,i use anothers 4:1 altlvds to sample input clk,Is this a right way?I know that the clk route throught global clk network,if I use clk as a signal ,it will be routed throught logic,will the performance be slower?
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Altera_Forum
Honored Contributor I
32 Views

The serializer that sends out the clock shouldn't be sampling the clock. Just tie off the 4 inputs to 1010 and you will send out a clock alongside your data. That should very nicely match your data output and you should have good timing.

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