FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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viterbi IP core problem

Honored Contributor II

When create viterbi IP core, we meet two error situations. 

First one:Carry out step two,generate simulation model and net list. When finish creating top - level schematic document, turn to create simulation model, and then get this error message. When we do not carry out step two, we can successfully create IP core.  



Second one: When change computer operating environment, the laptop and desktop computer use 13.0 and 13.1 version respectively, the system can normal running, but stopped in the following interface. We think may be the problem is the version of windows operating system. And then we use windows 7 and windows 10 respectively, then create the same result.  




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