Re: what is the circuit of 2^n -1

Altera_Forum · ‎11-13-2009

these is a problem for me,i need some help.

how can i use verilog describe 2^n -1

the input interface is input[3:0] n;

the output interface is output [15:0] result;

i know can use a table ,but these is some other describe

thanks

Altera_Forum · ‎11-13-2009

i am sorry my english is poor.

Altera_Forum · ‎11-13-2009

if it is just that simple you could write

module MyPower ( clk , In_N , Out_P );

input clk;

input [ 3:0] In_N;

output [15:0] Out_P;

reg [15:0] Out_P;

always @ ( posedge clk )

case ( In_N )

4'd0 : Out_P <= 16'd1;

4'd1 : Out_P <= 16'd2;

4'd2 : Out_P <= 16'd4;

4'd3 : Out_P <= 16'd8;

4'd4 : Out_P <= 16'd16;

4'd5 : Out_P <= 16'd32;

4'd6 : Out_P <= 16'd64;

4'd7 : Out_P <= 16'd128;

4'd8 : Out_P <= 16'd256;

4'd9 : Out_P <= 16'd512;

4'd10 : Out_P <= 16'd1024;

4'd11 : Out_P <= 16'd2048;

4'd12 : Out_P <= 16'd4096;

4'd13 : Out_P <= 16'd8192;

4'd14 : Out_P <= 16'd16384;

4'd15 : Out_P <= 16'd32768;

endcase

endmodule

but you could try to implement some kind of shift functionality

Altera_Forum · ‎11-13-2009

If I understood the question (4 to 16 decoder) then MSchmitt's coding is how I would implement this as well. If you don't want the decoder registered then you would write it like this:

reg [15:0] Out_P;

always @ (In_N)

begin

case (In_N)

4'd0 : Out_P = 16'd1;

4'd1 : Out_P = 16'd2;

4'd2 : Out_P = 16'd4;

4'd3 : Out_P = 16'd8;

4'd4 : Out_P = 16'd16;

4'd5 : Out_P = 16'd32;

4'd6 : Out_P = 16'd64;

4'd7 : Out_P = 16'd128;

4'd8 : Out_P = 16'd256;

4'd9 : Out_P = 16'd512;

4'd10 : Out_P = 16'd1024;

4'd11 : Out_P = 16'd2048;

4'd12 : Out_P = 16'd4096;

4'd13 : Out_P = 16'd8192;

4'd14 : Out_P = 16'd16384;

4'd15 : Out_P = 16'd32768;

endcase

end

Altera_Forum · ‎11-13-2009

First could you clarify? Are you trying to get:

a) (2^n)-1

or

b) 2^(n-1)

I suspect it's a). If not let me know.


module pow_2toN(
    input          n,
    output        result
);
wire     shift_reg;
assign  shift_reg   = {16'd0,16'hffff} << n;
assign  result      = shift_reg;
endmodule

or...

module pow_2toN(
    input          n,
    output        result
);
genvar i;
generate
    for(i=0;i<16;i=i+1) begin : result_assigns
        assign result = (i < n) : 1'b1 : 1'b0;
    end
endgenerate
endmodule

or...

module pow_2toN(
    input          n,
    output  reg   result
);
integer i;
always @* begin
                    result      = 16'd0;
    for(i=0;i<16;i=i+1)
        if(i<n)     result   = 1'b1;
end
endmodule

or...

module pow_2toN(
    input          n,
    output  reg   result
);
integer i;
always @* begin
    result      = 16'd1;
    for(i=1;i<16;i=i+1)
        if(i<=n)    result      = {result,1'b0};
                    result      = result + 16'hffff;
end
endmodule

We could keep going but I digress. I may have some typos in there. What might be entertaining for you is to try all these variants and see what wildly different compilation results they produce.

Jake

Altera_Forum · ‎11-13-2009

Oh Jake great , thats real fun to read and think about.

first example should be

assign shift_reg = {16'd1,16'h0000} << n;

to get the 1,2,4,8,... instead of 0,1,3,7,f,1f,...

It's realy a lesson worth to go through them all and understand them ...

Altera_Forum · ‎11-13-2009

As I stipulated, my assumption was that he wanted (2^n)-1. So the desired result would in fact be (0,1,3,7,f,...). If that assumption is incorrect then all of the examples need tweaking.

Jake

Altera_Forum · ‎11-14-2009

--- Quote Start ---

If I understood the question (4 to 16 decoder) then MSchmitt's coding is how I would implement this as well. If you don't want the decoder registered then you would write it like this:

reg [15:0] Out_P;

always @ (In_N)

begin

case (In_N)

4'd0 : Out_P = 16'd1;

4'd1 : Out_P = 16'd2;

4'd2 : Out_P = 16'd4;

4'd3 : Out_P = 16'd8;

4'd4 : Out_P = 16'd16;

4'd5 : Out_P = 16'd32;

4'd6 : Out_P = 16'd64;

4'd7 : Out_P = 16'd128;

4'd8 : Out_P = 16'd256;

4'd9 : Out_P = 16'd512;

4'd10 : Out_P = 16'd1024;

4'd11 : Out_P = 16'd2048;

4'd12 : Out_P = 16'd4096;

4'd13 : Out_P = 16'd8192;

4'd14 : Out_P = 16'd16384;

4'd15 : Out_P = 16'd32768;

endcase

end

--- Quote End ---

this is also a ROM

can it describe wtih register?

Altera_Forum · ‎11-14-2009

--- Quote Start ---

First could you clarify? Are you trying to get:

a) (2^n)-1

or

b) 2^(n-1)

I suspect it's a). If not let me know.


module pow_2toN(
    input          n,
    output        result
);
 
wire     shift_reg;
 
assign  shift_reg   = {16'd0,16'hffff} << n;
assign  result      = shift_reg;
 
endmodule

or...

module pow_2toN(
    input          n,
    output        result
);
 
genvar i;
generate
    for(i=0;i<16;i=i+1) begin : result_assigns
        assign result = (i < n) : 1'b1 : 1'b0;
    end
endgenerate
 
endmodule

or...

module pow_2toN(
    input          n,
    output  reg   result
);
 
integer i;
always @* begin
                    result      = 16'd0;
    for(i=0;i<16;i=i+1)
        if(i<n)     result   = 1'b1;
end
 
endmodule

or...

module pow_2toN(
    input          n,
    output  reg   result
);
 
integer i;
always @* begin
    result      = 16'd1;
 
    for(i=1;i<16;i=i+1)
        if(i<=n)    result      = {result,1'b0};
 
                    result      = result + 16'hffff;
end
 
endmodule

We could keep going but I digress. I may have some typos in there. What might be entertaining for you is to try all these variants and see what wildly different compilation results they produce.

Jake

--- Quote End ---

Hi jakobjones

I am sorry

it is (a)

assign shift_reg = {16'd0,16'hffff} << n;

Is this a RTL description?

Altera_Forum · ‎11-14-2009

Hi jakobjones

I want to know what is the circuit of the description

if you use synplify what above all?

Altera_Forum · ‎11-14-2009

If you have access to synplify, try the various implementations and see what circuits they produce.

Jake

Altera_Forum · ‎11-15-2009

--- Quote Start ---

this is also a ROM

can it describe wtih register?

--- Quote End ---

What I wrote wouldn't be synthesized as a ROM (in an Altera FPGA) since it's not synchronous. Instead you'll get the same muxing logic only the result isn't registered. Here is a good doc to take a look at to learn more about HDL coding styles and how they map to the FPGA logic: http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

The short forms using the shift operation I suspect will synthesize into the same multiplexer structure from the case statement. A variable shift operation (barrelshift) is a multiplexer of the same data under different shift distances. The shift amount maps to the select bits of the mux.

Like others have said try various codings and see if any give better results. It's easier to try various things and let synthesis do all the heavy lifting instead of the other way around :)

Altera_Forum · ‎11-15-2009

I don't assume significant differences in the synthesis results. The expression for each output signal should fit a 4-input -LUT, so it can be expected, that all logical equivalent descriptions end up in the same circuit.

Altera_Forum · ‎11-15-2009

--- Quote Start ---

What I wrote wouldn't be synthesized as a ROM (in an Altera FPGA) since it's not synchronous. Instead you'll get the same muxing logic only the result isn't registered. Here is a good doc to take a look at to learn more about HDL coding styles and how they map to the FPGA logic: http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

The short forms using the shift operation I suspect will synthesize into the same multiplexer structure from the case statement. A variable shift operation (barrelshift) is a multiplexer of the same data under different shift distances. The shift amount maps to the select bits of the mux.

Like others have said try various codings and see if any give better results. It's easier to try various things and let synthesis do all the heavy lifting instead of the other way around :)

--- Quote End ---

BadOmenthank you very much .

As you said,it will synthesize into the same multiplexer structure from the case statement

so if i interface a ROM

it can save so much resource ?

Altera_Forum · ‎11-15-2009

That is correct, you can use a small ROM as a lookup table based decoder. Just follow the ROM coding style in that link I posted. Keep in mind that this ROM will have a latency of one clock cycle.

Altera_Forum · ‎11-15-2009

A ROM is an option of course, but what do you mean with "save so much resource"?