whats the purpose of CRA slave port (control and status register ) of pcie hard IP ? what is the exact usage of this port.?

[anilinintel]

this is given as a optional port. but when i disable this. design sometimes may get hangup on the board and host gets stuck.

[Nathan_R_Intel]

​Hie,

The CRA Avalon-MM slave port provides host access to selected Configuration Space and status registers. Hence, accessing this selected Configuration Space when port is disabled could cause system to hand. For more details please refer to the documentation on CRA available in the user guide.

Regards,

Nathan

[anilinintel]

If this was the case, then it shouldn't be the choice for the user to enable/disable CRA port in platform designer GUI. Next,Any thumb rule of connecting this CRA to bar master ports.? let say im connecting bar2 to onchip memory and bar4 to EMIF ddr4 module, then from which bar this cra should connected to ? both 2 and 4 or only bar2.

[Nathan_R_Intel]

Hie,

I believe we should update the GUI to clearly describe when user needs to enable/disable the CRA port. Currently, it is covered in our user guide (link shown below in Table 15) mentioning this port is required for Requester/Completer variants and optional for Completer Only variant. I will take this feedback to the Quartus team.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_pcie_avmm.pdf

Actually, we do not have a guideline to connect CRA to BAR as we never expected this use case. CRA registers are accessible through AVMM.

Regards,

Nathan

[anilinintel]

Thanks for the reply. a little confused with your statement "Actually, we do not have a guideline to connect CRA to BAR as we never expected this use case. CRA registers are accessible through AVMM".

BARs are also a AVMM master ports.

The other thing is, CRA slave address that was shown on the platform designer was not used anywhere in the host driver c code. enabling this port matters alot to see pcie working smoothly.

[Nathan_R_Intel]

Oh sorry about the confusing statement. What I mean was, it is not a common use case whereby people access the CRA through BAR. Hence, we don't have a guideline on this.

Do you have any remaining questions?​

[anilinintel]

thanks. I am asking this one now because i wont get another person easily on the forum.

Now im with stratix 10 MX working with HBM2. whatever it was, i just see it as a memory just like ddr4 and onchip memory. (pcie + ocm) combo worked fine and verified pcie dma transfers , (pcie + ddr4 hilo module) combo verified n verified pcie dma transfers.

In the same manner i connected pcie to HBM2 where hbm2 got axi3/4. can i access hbm2 via pcie ?? I thought axi to avalon translation will take care by interconnect module, is that true ?. please answer me , if u are aware of it. otherwise that's it and thanks for the previous replies.

[Nathan_R_Intel]

Hie,

I am sorry , I am not familiar with the HBM2. Please repost your question in a new thread so others who are familiar with HBM2 could take a look at it.

Regards,

Nathan