About skew method for source synchronous input constrains in AN433?

[Lambert]

Hi everyone,

By viewing the training video, I have know how to set constrains of synchronous input constrains by skew method.

For the case : centre-aligned (rise-to-rise) SDR

I have one problem is that I don't know how the quartus II time analyzer to check setup and holdup relationship between data_in and clk_in by this information when I sample the data by clk_in directly? By theory, It think virtual and sample clk in fpga is edge_align, it will insert few delay at data and clk trace to satisfy the timing requirement. But if there's no relationship like figure one, how the result by getting from figure one to fit the case of figure two? In figure two, there's skew between virtual_clk and clk_in.

Best regards,

Lambert​

[BoonT_Intel]

Hello Sir,

It is ok as long as you have create clock for the input_clk in your constraint. To confirm on this, you can go to the time quest report, if you see the launch clock is virtual_clk and latch clock in input_clk, then it should be sufficient.

[Lambert]

Hi BCT_Intel,

I doubt that that there is skew between input_clk and dat_in in figure two, and I set constrains based on Virtual clk, and I don't give the relationship between virtual_clk and input_clk, do I can get the satisfy result according the constrains?

Best regards,

Lambert

[BoonT_Intel]

Hi Sir, I understand your concern. However, usually the skew between data in and input clock is small and can be ignore. Unless it is critical in your board design and you are seeing the big skew between data and clock. With this you can manually change the - wafeform value for the input clock create clock command to compensate the board skew.

create_clock -name input_clock -period 10 -waveform { 2.5 7.5 } [get_ports clk_in]

[Lambert]

Hi BCT_Intel,

If so, that makes me to make sure the trace fo the data and clk between device and FPGA have better to be the same length. And if the skew on the data pin and clk pin of the FPGA is very small, quartus will adjust the trace delay between clk and data to satisfy the timing according the skew information when edge-alignment and centre-aligned. In addition, I see that if I chose the method which puts the input clk to pll to generate sample clk by compensatory mode, in this method, the delay from data and clk pin to reg is almost the same, how quartus ii adjust the trace delay between data and clk to satisfy the timing?

Best regards,

Lambert

[BoonT_Intel]

In this case, you may use the set_input_delay to the data signal to compensate its skew relationship with clock in.

[Lambert]

Hi BCT_Intel,

I have one more question, if the skew between data in and input clk is small and can be ignore, is there necessary for us to set constrains? It will be okay that we can only set the clock constarins (liking creat_clock -name input_clock -period 10 [get_ports clk_in])?

Best regards,

Lambert​

[BoonT_Intel]

It is ok as long as you have the set_input_delay as explain above