Agilex 5 FPGA E-Series 065B Modular Development Kit - PINOUT Bank 6E, 6G, 6F, 6H

[robertzab]

Hi,

I have an Agilex™ 5 FPGA E-Series 065B Modular Development Kit, and I also created a project in which I intended to use pins from banks 6E, 6G, 6F, and 6H.

However, when I open Quartus and the Pin Planner, all the pins from these banks are shown as No Connect. I generated an I/O Banks report for the device A5ED065BB32AE4SR0, and these banks are not listed.

I am a bit confused because in the DevKit schematics, the IOs from these banks are routed, and the documentation on the website states that they can be used as HVIO.

Could you please clarify what is the status of these banks? Are they perhaps intended for migration to higher devices, such as Agilex 7?

Bert Regards,

Robert

[sstrell · Accepted solution]

It appears those banks aren't available on that density device.  Look at other pin tables under E series here to compare: https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html#agilex%E2%84%A25

Here's your pin out: https://www.intel.com/content/www/us/en/content-details/827729/pin-information-for-the-agilex-5-a5ed065b-device-xlsx-format-alt-format-pdf.html

It is odd that they are brought out to headers on that dev kit but probably because of the modular design of the kit.

[robertzab]

I based it on the schematics from the development kit. I was surprised when Quartus showed an error that it couldn’t assign that pin — because it doesn’t physically exist :).

Oh well, I consider the thread closed