We designed a custom board based on Arria V FPGA (5AGXMB1G4F40C5G).
Problem is with PCIe interface. this board is designed to have end point support, the link training is not happening with external root device. tried to put chip scope for PCIe Clock and observed no clock at all.
two clocks options provided for PCIe hard IP. the on-board generated 100MHz clock (LVDS) at Pins AE31 & AE32
and an external clock from root device board at pins AG32 & AG33 (HCSL).
Verified the hardware of on-board generated 100MHz clock by probing nearest possible points and the clock is available at PCBA upto via below FPGA balls (AE31 & AE32). attached those probed clocks and design details.
Please let me know what could possibly be issue here.
Do you have checked the Quartus project, how is the pin assignment.
From the background, I feel the clock itself is not coming means, may be Quartus Project issue.
Or the signal is not reaching to the FPGA .
FPGA team verified at their level don't see any issues. So we think may be package damaged or assembly issue (But xray reports shows BGA mounting is good)
We have one more 100MHz clock connected to pins C20 & D20 for DDR3. in chip scope we could able to see this clock.
Can this be used for PCIe interface as well.