FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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Can we able to operate system clock of FPGA with 25MHz or 50MHz input?

SKacc
Novice
271 Views

Arria V Device Overview(AV-51001) says the input reference clock ranges from 27MHz to 710MHz.

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3 Replies
AnandRaj_S_Intel
Employee
109 Views

Hi Srikanth,

 

Yes, you can have a 25 MHz or 50 MHz system/global clock for FPGA. And use PLL to generate the required clock frequency for other design modules (ddr/transceivers/ADC).

Refer respective datasheet under the clock-tree session.

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Regards

Anand

SKacc
Novice
109 Views

Datasheet says global or regional clock frequency is either 625 or 525 MHz only. (Document ref: AV_51002, Page No 44).

AnandRaj_S_Intel
Employee
109 Views

Hi,

 

That is a max frequency that you can have for the global or regional clock.

  1. You can have a 25 MHz or 50 MHz system/global clock for FPGA. And use PLL to generate the required clock frequency for other design modules
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