Using DE2-115 with NIOS II processor (/f option). Also using unmodified TERASIC component. Have a simple SW application to write/read SRAM. WOrks approx 95% of time. I saw a brief note that the SRAM wait states required changes if using the higher speed CPU. Could someone confirm. Am using 2RD, 2 WR, 1 HOLD and 1 SETUP. Please advise if there is a better arrangement.