Different behavior on different CPLDs

[MHamz1]

I am using the MAX V series CPLDs, I am experiencing different behavior of same RTL on the different models of MAX V CPLDs,

My RTL works fine on "5M570ZF256C5" but when I port the same onto "5M570ZT100A5N" the behavior gets changed completely.

I have attached the State Machine where I am facing the issue

CONFIGURE_ADC : process(clk) is TYPE StateMachine IS(Init,D1,T1,B1,D2,T2,B2,D3,T3,B3,D4,T4,B4,Stop,Delay,Restart); --state machine data type VARIABLE SPIState : StateMachine := Init; --State machine variable variable fifo_memory : fifo_memory_type := (X"00",X"03"); variable read_memory : read_data_type := (X"00", X"00", X"00", X"00"); variable fifo_head : integer range 0 to 1 := 0; variable read_head : integer range 0 to 3 := 0; variable mux_flag : integer range 0 to 1 := 0;; begin if rising_edge(clk) then --if(microseconds > 3000000) then case SPIState is when Init => if(mux_flag = 0) then fifo_memory(0) := X"04"; --fifo_memory(1) := X"03"; mux_flag := 1; SPIState := D1; else fifo_memory(0) := X"34"; --fifo_memory(1) := X"03"; mux_flag := 0; SPIState := D1; end if; when D1 => fifo_head := 0; cs_n <= '0'; if(busy_transfer = '0') then read_head := 0; read_memory(read_head) := spi_rx_data; spi_tx_data <= fifo_memory(fifo_head); SPIState := T1; end if; when T1 => trigger_transf <= '1'; SPIState := B1; fifo_head := 1; when B1 => if(busy_transfer = '1') then trigger_transf <= '0'; SPIState := D2; end if; when D2 => if(busy_transfer = '0') then read_head := 1; read_memory(read_head) := spi_rx_data; spi_tx_data <= fifo_memory(fifo_head); SPIState := T2; end if; when T2 => trigger_transf <= '1'; SPIState := B2; when B2 => if(busy_transfer = '1') then trigger_transf <= '0'; SPIState := D3; --cs_n <= '1'; end if; when D3 => if(busy_transfer = '0') then read_head := 2; read_memory(read_head) := spi_rx_data; spi_tx_data <= x"00"; SPIState := T3; end if; when T3 => trigger_transf <= '1'; SPIState := B3; when B3 => if(busy_transfer = '1') then trigger_transf <= '0'; SPIState := D4; end if; when D4 => if(busy_transfer = '0') then read_head := 3; read_memory(read_head) := spi_rx_data; spi_tx_data <= x"00"; SPIState := T4; end if; when T4 => trigger_transf <= '1'; SPIState := B4; when B4 => if(busy_transfer = '1') then trigger_transf <= '0'; SPIState := Stop; --cs_n <= '1'; end if; when Stop => if(busy_transfer = '0') then cs_n <= '1'; SPIState := Delay; end if; when Delay => counter <= counter + 1; if(counter >= 3000000) then SPIState := Restart; counter <= X"00000000"; cs_n <= '0'; end if; when Restart => if(miso = '0') then SPIState := Init; end if; when others => null; end case; --end if; end if; end process CONFIGURE_ADC;

[sstrell]

Can you explain what the difference in behavior is? There's no way to answer your question otherwise.

#iwork4intel

[MHamz1]

Thank you for your reply, basically this is a SPI Master State machine

In case when it works fine, it transmits 4 bytes of data continuously after a given delay

After porting it on the 5M570ZT100A5N the behavior becomes unpredictable, it sometimes transmits 2 bytes and stops for ever, sometimes it transmits 3 bytes and stops for ever, sometimes it transmits well for a duration of say 30 seconds and then stops.

I have no clue about the issue right know.

[sstrell]

Do you have simulation or Signal Tap data to show what exactly you are seeing? Or it could be a timing issue. Can you post your .sdc file?

#iwork4intel

[MHamz1]

I will share the .sdc file shortly with you

[SreekumarR_G_Intel]

I assume clock rate is same between old and new device.As Steven said you can load the sdc file and check the timing slack in the timing analyzer. Could you post the timing report as well ? Thank you , Regards, Sree

[MHamz1]

Thank you for your reply , Yes the clock speed is same in both devices, I am able to solve the problem by an alternate way i.e by replacing some SIGNALS with VARIABLES however i am still unclear that what is the problem in using SIGNALS,

I will share the sdc file shortly with you

[MHamz1]

------------------------------------------------------------

Timing Analyzer Summary

------------------------------------------------------------

Type : Setup 'CLK'

Slack : -26.114

TNS  : -5667.650

Type : Hold 'CLK'

Slack : 1.728

TNS  : 0.000

Type : Minimum Pulse Width 'CLK'

Slack : -2.289

TNS  : -2.289

------------------------------------------------------------

[MHamz1]

------------------------------------------------------------

Timing Analyzer Summary

------------------------------------------------------------

Type : Setup 'CLK'

Slack : -26.114

TNS  : -5667.650

Type : Hold 'CLK'

Slack : 1.728

TNS  : 0.000

Type : Minimum Pulse Width 'CLK'

Slack : -2.289

TNS  : -2.289

------------------------------------------------------------

[MHamz1]

Unfortunately I do not have .sdc file, how can i create it

[SreekumarR_G_Intel]

sorry , got into other issue and couldnt able to reply timely ,

About the Signals and variables ,

There are lot of difference using signal and variables in RTL and one important difference is Variable assign the values immediately whereas signals depends on the logic use in the RTL (I.e mean combo or seq) . if Combo immdeiately assign it where as seq based on the logic it might take one /couple of clock cycles.

It is easy to understand if you create the test bench and see the RTL behavior in modelSIM.

About the timing , It looks really bad :(.Did you included the clock constraint ?

I am not sure what iam missing since both the CPLD from the same family and speed grade of the device are also same. here is what one more question Can you check the pin assignment since both are different package ? Also check the clock you connected to the global clock pins.

Thank you,

Regards,

Sree