Error while Custom Component Importing to Qsys

[TBaki]

I just added custom VHDL component in qsys. The module is just AND gate logic. I'm using quartus 13.1 version I'm getting error as,. Error: No modules found when analyzing null.

[Nurina]

Hi,

In this version of Quartus, if there was any error in your code, that error message would be all the Component Editor would display, which can be difficult for debugging. (this is a known bug that since been fixed in v17.1 https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/2017/error--no-modules-found-when-analyzing-null.html)

Have you tried synthesizing the code directly in Quartus instead of through Qsys? It would provide detailed messages on any issues with the code. Once fixed, you can take it back through Qsys to build the component.

Another solution is to just migrate to a later version of Quartus where this issue is fixed.

Regards,

Nurina

[TBaki]

The module got synthesized in quartus. I can't migrate to other version as I'm using Cyclone III FPGA. Higher version quartus won't support this FPGA

[Nurina]

Hi,

So after synthesizing on Quartus you tried to compile it on Qsys and only came across a problem there?

Do you get any error or warning messages on Quartus?

Regards,

Nurina

[sstrell]

Can you post the code?

[TBaki]

Quartus II 64-Bit Version 13.1.0 Build 162.

Error is Error: No modules found when analyzing null.

[sstrell]

You have a semicolon at the end of 

b : out std_logic

Remove the semicolon and you should be good to go.

Sidenote: technically this is a register, not an AND gate.

[TBaki]

Still not got fixed. 

[sstrell]

It's blocked in your screenshot, but is the top-level module set correctly there on the Files tab in the Component Editor (as the error mentions)?

[TBaki]

What you mean by component editor in Quartus II 64-Bit Version 13.1.0 Build 162?

[sstrell]

The Component Editor is the tool you're using in the screenshot to create the custom component.

[TBaki]

Ok. Yes I selected top level. It didn't work. 

[Nurina]

Hi,

Can you try analyze the HDL file again? I've tried to replicate your error and the problem is solved after removing the semicolon.

Regards,

Nurina

[TBaki]

Hello,

May I know which version of quartus tool you used. I used Quartus II 64-Bit Version 13.1.0 Build 162. Possible to share your .qpf file please

[Nurina]

Hi,

I used Quartus Prime Version 17.1. I believe that if it's analyzed correctly here it should be the same in v13.1 as well. 

I've attached the .qar file here.

Regards,

Nurina

[TBaki]

Hi, 

Version 15, 16 17 ..it will work. Try with version I mentioned. With version 16 it worked for me. 13.1 didn't work. so posted the query. Thanks

[Nurina]

Hi,

Can you try remove 'is' after 'process(clk)' and see if there's a difference there?

Thanks,

Nurina

[TBaki]

Hi, 

Removed 'is'. But, no luck

[Nurina]

Hi,

Can you try put parentheses after your first if statement like so

if (rising_edge(clk)) then

additionally try with and without the 'is' from my previous reply.

Thanks,

Nurina

[TBaki]

Hello,

I tried but didn't work

[Nurina]

Hi,

I tried on Quartus II 64-Bit Version 13.1.0 Build 162 and it seems to work fine. Could you take a look?

Regards,

Nurina