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Hi all,
I am trying to integrate UDPIP IPCORE of CAST Inc with TSE MAC on StratixIII Dev Board in GMII interface but not succeeded. The board Led status are as follows. Link speed led- D8 is glowing Duplex led - D9 is glowing. RX led(D15) is blinking but TX led(D14) is not blinking. when i probe the signal coming from phy on signal tap nothing is coming(even rx_clk). I am connecting enet_gtx_clk(125Mhz) from FPGA to Phy and Tx_clk(125Mhz) from FPGA to PHY. When i swith 10/100 link ,ethernet link speed led switching accordingly so i think phy is behaving. but in GMII interface nothing is coming. please help me,i tried SR also but not resolved. with regards J S HyankiLink Copied
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Is it Marvell 88E1111 chip on the board? Did You do correct RESET sequence for the chip? Are all timings met?
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Hi socrates,
Please tel me what is the reset sequence of PHY to make it on GMII interface. with regards J S Hyanki- Mark as New
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The reset sequence is described in 88E1111 datasheet.
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Hi socrates
if you have data sheet of 88E1111 please give me. with regards J S Hyanki- Mark as New
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I do, but it's under NDA. Maybe Altera could help here?
Anyway, do at least 16 bits timeout timer on reset signal and reset phy after power up. Keep reset active for a few miliseconds.- Mark as New
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Hi socrates,
As i gone through the TSE MAC document i did't find the how TSE MAC will initiate the MDI interface. I think by accessing the TSE MAC configuration, MDI interface works automatically or i have to make seprate logic for it. with regards J S Hyanki- Mark as New
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Forget the GMII and MDIO lines. We are talking about RESET signal to the PHY itself.
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Hi socrates,
there is RESET pin of PHY and MDI pin of PHY. so i think i should reset through reset pin only. with regards J s Hyanki- Mark as New
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--- Quote Start --- Hi socrates, there is RESET pin of PHY and MDI pin of PHY. so i think i should reset through reset pin only. with regards J s Hyanki --- Quote End --- Exactly. The reset through MDIO will be done in software later.
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Hi socrates,
I don't have document of phy that's why i am not knowing the hard reset sequence. with regards J S Hyanki
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