FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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I have generated an example design for PCIe , which is targeted for Stratix 10 DX development kit. I tried the simulation on Modelsim PE edition with scripts generated by Quartus pro. Attached error of simulation. please help fix the issue.

VMR001
Beginner
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Attached snapshot of the error message reported by the modelsim pe edition tool.

 

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BoonT_Intel
Moderator
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Hello Sir,

I don't see any attachment in this thread.

May I know are you running the P-tile PCIe IP? For P-Tile, its only support for simulation using VCS simulator.

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VMR001
Beginner
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Thank you for quick response. Yes we are using P-tile PCIe IP. Will there be support for Riviera or Modelsim/Questasim any time soon

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BoonT_Intel
Moderator
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unfortunately, there is no plan to support for other simulator.

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