No instance found - Stratix 10 GX L-tile dev board

[Yifeng]

Hi all,

I have encountered a problem that any services related to JTAG of this Stratix 10 FPGA cannot be accessed. For example, when compiled with Signaltap, see Fig.1 and Fig.2, it shows "Instance not found", even if in the Project Navigator, the SignalTap is synthesized in auto_fab and the correct sof file was programmed.

In the design, I have included a "JTAG to Avalon Master Bridge" in the qsys, which is not accessible neither, in Fig3. As a reference, the other devices (Arria5 and Arria 10) connected to this PC can be recognized with their JTAG nodes, but this Stratix 10 (with JTAGID=C32150DD) doesn't show up any JTAG service, to cross-check which is not discoverable through tcl: `set masters [get_service_paths master]`. When I tried to link the device to my top.sof, it prompts error as "Device has different visible SLD agents".

The Stratix 10 FPGA is correctly programmed and showed correct Device Name under Programmer, in Fig.4. It can be confirmed by Configuration Debugger, in Fig.5 and 6, which also describes part of my settings.

The design I am using is close to the reference design for this dev board (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/stratix/10-gx-signal-integrity.html) `stratix10GX_1sg280uf50_si_revd_v18.0b219_v1.0 (qts_sma example)`. Since the reference is for ES, the board I have is Production Version, several settings has been adapted (PMBus/VID etc). The Qsys in exported as tcl from reference design and generated again in the new project with Quartus 23.1.0 Build 115.

To conclude, the board can be programmed normally with LED blinking and (maybe, to be measured) L-hile configured as designed, but JTAG services (SigntalTap and JTAG-AVMM host) are not discoverable.

As a side note:

1) I have tried with the built-in USB Download Cable on board and external ALTERA USB BLASTER I, and turns out both didn't work.

2) The Device Name is NOT recognized everywhere except in the Programmer.

3) I didn't use any PR (Partial Reconfiguration) in the design, so I assume the JTAG HUB and JTAG Node can be connected automatically.  Using the SLD Bridge Agent and Host to cross the region is not necessary. I noticed auto_fab_0 has Design Partition Type set to "Default".

4) I may have overlook some small settings, since I am new to Quartus Pro.

Thank you very much for any suggestions!

Best,

YifengFig.5Fig.6Fig.4

Fig.3

Fig.2  Fig.1

[sstrell]

In Signal Tap, what is that device you've selected on the right ("@1: {0xC32150DD}")?  Is that the S10 or another device on the JTAG chain?  If you've selected the wrong device, then Signal Tap obviously will not work correctly.  You could also try programming the device from Signal Tap instead of the Programmer.

Looking at System Console, yeah you're accessing the wrong device on the chain.

[Yifeng · Accepted solution]

Dear sstrell,

I checked the S10 on this dev board has this JTAGID(0xC32150DD), so I am not programming the wrong device. But actually, you remind me of checking the switches for configuration flow on our dev board, because the configuration chains are JTAG: PC->USB-PHY->MAX10->S10/MAX_V or FLASH, AvSTx32: MAX_V->S10.

The switches for config was set correctly. As a check, I toggled the switch and used JTAG to re-programmed MAX_V with the max5 sof from design reference, then the problem is solved. The strange thing is I have never tried to program MAX_V , because it can load factory firmware to S10 and let S10 display something on LCD screen, therefore I assume MAX_V works out-of-box.  And, (JTAG) chain will not include MAX_V if I toggle the switch on MAX10 to only-select S10, but it turns out that MAX_V has been interfering with JTAG out-going signals going into MAX10 even if MAX_V was not selected, which explains that downloading configuration to S10 works fine, but not all JTAG communications is functional (only JTAG ID showed up, but not Device Name).

Now, I can access use all the JTAG services on S10 normally. Thanks for your suggestions.

Best,

Yifeng

[Farabi]

Hello,

Can you share your .stp file? we can take a look.

regards,

Farabi

[sstrell]

Weird, but glad you found a solution!

[NurAiman_M_Intel]

We are glad that you have found the solution!

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