Porting design to T0117 from XpressGX5LP-HE, both with 5SGXEA7K2F40C2N

[M3511]

I am looking to port a design to the T0117 from the XpressGX5LP-HE. Both have the 5SGXEA7K2F40C2N chip. I understand the pins are different and I will need to re-assign them appropriately, but are there additional issues I should be aware of? I'm only using 1 QSFP+ interface as 4x10Gbps interfaces.

My pin mappings are below

# Pins Assignments

set_location_assignment PIN_AF6 -to clk644M
set_location_assignment PIN_AK23 -to clk125M
set_location_assignment PIN_AV29 -to clk50M
set_location_assignment PIN_N14 -to pushbutton_rstn
#------
# ethernet
#------
set_location_assignment PIN_AF25 -to eth40g_rstn
set_location_assignment PIN_AH27 -to eth40g_int
set_location_assignment PIN_AE26 -to eth40g_modsel
set_location_assignment PIN_AD26 -to eth40g_lpmode
set_location_assignment PIN_AH25 -to eth40g_modprsn
set_location_assignment PIN_AF26 -to eth40g_scl
set_location_assignment PIN_AG25 -to eth40g_sda
#-------
# ethernet 4 * 10g
#-------
set_location_assignment PIN_AU4 -to eth40g_tx[0]
set_location_assignment PIN_AV2 -to eth40g_rx[0]
set_location_assignment PIN_AR4 -to eth40g_tx[1]
set_location_assignment PIN_AT2 -to eth40g_rx[1]
set_location_assignment PIN_AN4 -to eth40g_tx[2]
set_location_assignment PIN_AP2 -to eth40g_rx[2]
set_location_assignment PIN_AL4 -to eth40g_tx[3]
set_location_assignment PIN_AM2 -to eth40g_rx[3]

set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_instance_assignment -name IO_STANDARD LVDS -to clk644M
set_instance_assignment -name IO_STANDARD LVDS -to clk125M
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to eth40g_tx
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to eth40g_rx

[CheePin_C_Intel]

Hi,

As I understand it, you have some pinout inquiries related to design migration. the SV device - 5SGXEA7K2F40C2N. From your description, you seems to mention that both design is having the same SV device (5SGXEA7K2F40C2N) but the pins are different. Sorry for any confusion. Would you mind to further elaborate on the pin difference since the SV part is the same?

Also, please help to furhter elaborate on what is the "XpressGX5LP-HE" that you are referring here? As I looked in to the manual attached, it seems like the manual is not something from Intel.

Please let me know if there is any concern. Thank you.

[M3511]

The "XpressGX5LP-HE" is a 3rd party board built with the 5SGXEA7K2F40C2N. Therefore different pin names for the mapping correspond to the transceivers for example QSFP_MOD_SELn is AG27 on the intel Development board, but AE26 on the XpressGX board.

Do you know what the dimensions of the Stratix V GX FPGA Development Board are with the fan mounted? (how far 'up' it reaches) Can it be placed in a typical x8 PCIE full height server slot?

[CheePin_C_Intel]

Hi,

Thanks for your update. Regarding your latest inquiry on the dimension, sorry as I do not have further insight into it. Would you mind to help opening a new case with title specifically on dimension of devkit. You then let me know the case so that I could highlight to our devkit team.

Please let me know if there is any concern. Thank you.

[CheePin_C_Intel]

Hi,

Regarding your migration to SV devkit, please feel free to let me know if you encounter any Fitter/placement problem so that I could further assist.

Please let me know if there is any concern. Thank you.

[CheePin_C_Intel]

Hi,

As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.