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Simulating by ModelSIM on quartus|| 9.0 - XOR function bus_signals error in verilog file

Savino
初学者
734 次查看

Good evening everyone, for several hours I have been running into a problem using quartus|| 9.0 and ModelSim.

I have created a very simple project with a bus input and a bus output, and an XOR function inside. The program synthesis is successful and so is the simulation. Unfortunately, as soon as I try to simulate the program via ModelSIM an error appears. Basically:
- given the program written and compiled with a .bdf file
- I create the .hdl file (so I delete the .bdf file)
- as soon as I launch the RTL simulation, a syntax error appears in the file automatically created by quartus|| as follows:
assign out = in[29:0] ^ {in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in}[30];
if I try to perform the XOR operation between non-bus data (single data) I have no error. It seems that the XOR function between multiple data such as data buses generates this error. Is there a solution?
I attach the project.

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ShengN_Intel
员工
628 次查看

Hi Savino,


I misunderstood the situation. As mentioned by sstrell, the input must be same width. Using same width will be no problem.

You're using different width, that's why causing the bug.


Thanks,

Regards,

Sheng


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sstrell
名誉分销商 III
660 次查看

An XOR between a bus and a single signal makes no sense.  The bus widths must match to perform a bit-by-bit XOR operation.

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ShengN_Intel
员工
644 次查看

Hi,


Please change this assign out = in[29:0] ^ {in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in,in}[30]; to this assign out = in[29:0] ^ in[30];


Thanks,

Regards,

Sheng


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Savino
初学者
639 次查看

Hi, I tried all the combination without succes and at the end i used more xor gate for each single data, like attached and i fixed the issue but if is possible do the xor operation in one shot for me is better (like at beginning working with bus data)

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ShengN_Intel
员工
629 次查看

Hi Savino,


I misunderstood the situation. As mentioned by sstrell, the input must be same width. Using same width will be no problem.

You're using different width, that's why causing the bug.


Thanks,

Regards,

Sheng


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Savino
初学者
569 次查看

okay, tks for fdk

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