Structure of Cyclone Ⅴ and EPCQ-A

[NAika]

I am trying to realize the Cyclone V configuration using EPCQ-A(AS Mode).

EPCQ-A

 Output Delay(tCLQX) min 1.5ns

Cyclone V

 Input hold time(tDH) min 2.9ns

Could you tell me what kind of connection method is there?

(CR etc...)

[NAika]

The DCLK pin can not be connected directly with Spec specified below.

EPCQ-A

 Output Delay(tCLQX) min 1.5ns

Cyclone V

 Input hold time(tDH) min 2.9ns

Could you tell me what kind of connection method is there?

(CR etc...)

[a_x_h_75]

Good spot. I think the datasheet for the EPCQ device is misleading. I think the problem is that Intel/Altera always capture the figures from the FPGA's point of view - if that makes sense (I'm not sure it does...)

Refer to figure 53 (page 95) of the equivalent Micron part. All timings, and in particular t_CLQV & t_CLQX are with respect to the rising edge of the clock:

https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_l_512_abb_0.pdf

Given data is latched into the FPGA on the falling edge of DCLK I think perhaps Intel/Altera have tried to reference the same edge in the memory device's datasheet when, I suspect, they're no different to the Micron (or other 3rd party) devices.

Cheers,

Alex

[Nooraini_Y_Intel · Accepted solution]

Hi NAika,

You can follow the guideline under chapter “1.4 Evaluating Data Setup and Hold Timing Slack” in AN822 to evaluate the data hold time slack on your board in order to ensure you are meeting the Cyclone V data hold time (tDH) requirement.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an822.pdf

Also, you can refer to the following KDB for other recommendation that you can consider for Cyclone V AS configuration board design:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/component/2018/why-does-cyclone-v-as-configuration-with-epcq-epcqa-devices-fail.html

Regards,

Nooraini

[NAika]

Thank you for answer.

We will consider it.