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timing in I/O pads

fxu001
Novice
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Hello,

 

Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any recommandation or hint about this topic in FPGA design? It is a great if your suggestion can help me to pass I/O timing.

Again Thank you in advance!

 

-Fred

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fxu001
Novice
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HI YY, I see. Thanks for your quick response. Currently I add new commands in qsf file as following as: set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataL[2]" set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataL[0]"ā€‹ set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataH[3]"ā€‹ set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataL[1]"ā€‹ set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataL[6]"ā€‹ ā€‹ set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataH[6]"ā€‹ set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataH[2]"ā€‹ set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataH[0]"ā€‹ set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataL[3]"ā€‹ set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataH[1]" The timing report is still has [cid:cdf2b8ff-bd8b-41ee-9023-b788567e7ff3] The floorplan placement which matches constrain as following as [cid:74445102-84c9-44b8-a9af-dc4882e6e8be] Before I put above constraints, the floorplan placement is as below routing with same report delay, but routing distance cross a lot of LABs comparing above and below placement, so I suspect timing report is wrong. As I did Synopsys ICC2 timing project back three years ago, these distances should have different timing report because net delay has a big difference. Since I/O pads fix the location, you can figure out rest of constrains to do experiments. [cid:7fd1c7c8-fc24-4aac-9c3e-92c450438757] ā€‹ I used 10AX027H4F34I3SG device. Thank you so much! -Fred
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KhaiChein_Y_Intel
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ā€‹Hi Fred,

 

Are you attaching something in this thread? I cannot see the attachment. Could you re-attach?

 

Thanks.

Best regards,

YY

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fxu001
Novice
233 Views
Hi YY, On. Never mind, maybe system block them. Thanks, -Fred
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KhaiChein_Y_Intel
233 Views

Hi Fred,

 

Do you have any other questions or help needed?

Thanks.

 

-YY

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fxu001
Novice
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Hi YY, I am pretty smooth to debug this FPGA so far. I only have one question: do you know or ever hear that Altera FPGA can increase sensitivity for the LVDS input pin beside board to change terminator or layout trace width or length. I already turn on LVDS terminator. I ask this question because one of bit_clock signals is too weak that cause miss detect data frequently. Besides, I am fine now. Thanks, -Fred
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fxu001
Novice
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Hi YY, Oh, I think I might change design architecture to solve this unstable issue in the FPFA if you cannot find a solution in the device side, but I need to do some experiments in the next week to confirm what I thought since I need to solve more important issue in another topic during this design. If you would like to close this case, please do it. Again thank so much for your supportšŸ˜Š Thanks, -Fred
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KhaiChein_Y_Intel
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You are welcome. šŸ˜Š

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