Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any recommandation or hint about this topic in FPGA design? It is a great if your suggestion can help me to pass I/O timing.
Again Thank you in advance!
It's great to hear that.
You may use
Tools > Chip Planner to analyze and modify the placement of resources.
Assignments > Pin Planner to easily make assignments to device I/O pins within a graphical representation of the target device. The Intel® Quartus® Prime software uses these assignments to place and route your design during device programming.
Assignments > Assignment Editor to view, create, and edit assignments.
If you open the Pin Planner (Assignments > Pin Planner), you will see the pins for each bank are colored differently. You may find the region that you want and select the pin, the pin number will appear under pin properties.