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Novice
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timing in I/O pads

Hello,

 

Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any recommandation or hint about this topic in FPGA design? It is a great if your suggestion can help me to pass I/O timing.

Again Thank you in advance!

 

-Fred

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Hi fxu001,

 

Can you provide the design, timing report and sdc for investigation?

 

Thanks.

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Novice
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Hi YY, I don’t ASML policy, so I cannot give you the design files. Timing report and sdc files should be fine. Which file for the timing? Would you think it is useful if you don’t have design file to solve this issue? Can you image which ways you can solve the issue without these files. As I know Synopsys did support without design files in lot of cases since I stay there for a long time, can you image to solve this issue? The reason that I raise this issue because bank 3C timing has huge different with another bank 3D when I use GPIO cells. I use the device which is 10AX027H4F34I3SG. In addition, as I remember when I did Xilinx FPGA in Cisco, I used “loc” command to fix the I/O timing in the IOB cell. Do you have similar methods in Altera, so I can bypass the issue? Thanks, -Fred
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Novice
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Hi YY, If I know how to lock the location floorplan editor, I can alternatively bypass the IO pads timing issue in the system; otherwise, the system will be unstable because timing which I don’t like that scenarios. Thanks, -fred
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Hi fxu001,

 

For LOC equivalent assignment , you may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an307.pdf ( Chapter 4.3.2 Table 57)

 

Thanks.

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Novice
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Hi YY, Great info. Next step is how to open the floorplan editor which it is equivalent Xilinx tool, so I can check the location and lock them; then, I check the timing. BTW, I solve the timing different in the different I/O banks; basically I evenly distribute AV bus during feed into JESD204B IP. I am close to reach timing in the I/O pads, but I still need to understand Altera tool. Internal timings are okay. Thanks, -Fred
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Hi YY, BTW, can you help me to ask JESD204B designer what 8B/10B protocol does he/she use in the RTL since I cannot figure out the output pattern because RTL in that portion is encrypted? I can find out 10B in the serial bus based on tx_link_clk_clk clock cycle, but no matter how to shift location, and I cannot find the pattern matches Wikipedia 8b/10b encoding. Maybe he/she jump to use. Since I cannot access IEEE JESD204B std, is it possible to give me some hint? He/she can give me the example during input is 0 (zero) in the JESD204B AV bus and what do expect value output in serial bus. From I analyze your JESD RTL and waveform, I think what he/she design way is feed 64 bus through JESD204B AV bus; then, the logic split up and low 32 bits bus. After that, the serial bus will first send out low 32bits through 8b/10B and converted to 40bits. From the RTL, he/she uses the little endian tech. I also file the case for 8b/10b issue. Thanks, -Fred
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Hi YY, Don’t bother about 8B/10B issue since I found solution from EEtimes which it started K28.5 parameters with RD=-1 and RD=+1 with repeat pattern. Thanks, -Fred
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Hi Fred,

 

It's great to hear that.

You may use

Tools > Chip Planner to analyze and modify the placement of resources.

Assignments > Pin Planner to easily make assignments to device I/O pins within a graphical representation of the target device. The Intel® Quartus® Prime software uses these assignments to place and route your design during device programming.

Assignments > Assignment Editor to view, create, and edit assignments.

 

Thanks.

Best regards,

YY

 

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Novice
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Hi YY, Great. Please wait until middle of next week since I will do the experiments about end of week. If anything that I confuse, I will send you an email; otherwise, please close this issue in the middle of next week. Thank you so much for your quick response. Thanks! -Fred
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Novice
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HI YY, Do you know where the GPIO cells close to 3C and 3D I/O pins regions in device 10AX027H4F34I3SG? Thanks, -Fred
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Hi Fred,

 

If you open the Pin Planner (Assignments > Pin Planner), you will see the pins for each bank are colored differently. You may find the region that you want and select the pin, the pin number will appear under pin properties.

 

Thanks.

Best regards,

YY

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Novice
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Hi YY, I did not answer my question. My question is “do you know the GPIO location close to 3C and 3D I/O pins regions in device 10AX027H4F34I3SG?” The question is to emphasize GPIO cells, I/O regions and device. Could you spend some time to check the device info; then, you will find detail location. Thank you in advance! -Fred
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Novice
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Okay, I give you a little bit simple question. How to find out ALL GPIO location in X-Y coordination?
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Hi YY, I changed GPIO clock to source sync, and data timing reduce from 2.7 to 0.9 for WNS. The TNS also reduce a lot. If we can find a way to turn GPIO data timing, we might solve the issue. DO you have any suggestion? Thanks, -Fred
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Hi Fred, Here is the Pin-out file: https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html Thanks. Best regards, YY
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Hi YY, Thank you so much for your information, and I will review it. From Chip editor, I saw the GPIO very close with its pin which it is in the same IOB block, so manually move the cell option is gone. I read your link about Xilinx with Altera comparison paper, and I found there is one option for the compiler setting for three options. Currently I put default, so I would like to try aggressive option. However, I meet memory issue again … Thanks, -Fred
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Hi YY, Based on you gave me the application note 307 on page 77, I added QSF command as following as: set_instance_assignment -name PLACE_REGION "X126 Y58 X148 Y71" -to five_adc1_data set_instance_assignment -name RESERVE_PLACE_REGION -to five_adc1_data​ set_instance_assignment -name CORE_ONLY_PLACE_REGION -to five_adc1_data​ set_instance_assignment -name REGION_NAME five_adc1_data -to five_adc1_data​ set_instance_assignment -name ROUTE_REGION "X126 Y58 X148 Y71" -to five_adc1_data The above commands partially working because some logic placed that region now which previous this region is empty (you can open chip editor to reference my X-Y location to figure out in device 10AX027H4F34I3SG), so I think your R&D instantiated Synopsys command something like "create_placement_blockage -type soft". Would you know what is command for "-type hard" which I want to force them to go to different region? If it is already "hard", it seems a BUG in that condition. The reason is that current LAB is far away with GPIO which located left above location that cause the timing violation, and your Altera parse prefers that location even I put above QSF command, but this placement causes my timing problem in my case. Please see the attachment for the arrow points for net connections. Again I can not give you testcase, but all necessary info I already explain for the R&D debug. It is urgent, and please ask your R&D puts some effort since my board will come back next week. This is the only problem that I can image now, so please help me:) Thank you so much in advance. [cid:a5d0808e-0e28-4c4a-b3c0-c0611c773be9] Thanks, -Fred
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Hi YY, How to interpret FF_X149_Y78_N16 for number of 16? How about I have LAB_X149_Y72_N0 convert to FF_X149_Y72_N?? what is tool behavior? Thanks, -Fred
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Don’t worry about this issue and I know how to interpret the LAB location now, but I don’t know why timing report didn’t change. As I know Synopsys timing report should change even some 10 pico second change. Could do some experiment in your side with any small testcase? I really feel wired for the timing report even I locked different location. Thank you in advance! Oh the command is set_location_assignment is hard lock
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