Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any recommandation or hint about this topic in FPGA design? It is a great if your suggestion can help me to pass I/O timing.
Again Thank you in advance!
I am sorry for the late reply. We have Public holiday after the weekend.
What kind of experiment you would like to do? May I know the changes you have made and the result that you think is not expected. Sure. You may provide the testcase and let me know the steps and expected result.