High-Speed Transceiver Demo Designs - IV-series (StratixIV GX)

High Speed Transceiver Demo Designs - IV - Series (StratixIV GX)

For a list of Stratix 10 GX High-Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Stratix-10-GX-Series/ta-p/735749
For a list of Stratix 10 TX High-Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Stratix-10-TX-Series/ta-p/735133
For a list of Arria 10 High Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Arria-10-Series/ta-p/735131
For a list of V-Series (SVGX, AVGT, AVGX, and CVGX) High-Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-V-Series-StratixV-ArriaV-and/ta-p/735783

Stratix IV GX

Recovered Clock Generation and System Clock Generation using GPLL (no cascading)

Stratix IV GX SI board: 1 Channel 64b66 encoded design at 6.25Gbps with creation of recovered clock and system clock through GPLL

GXIV_SIBoard_1Ch_64b66b_Clock_Recovery_GPLL.zip

Recovered Clock Generation for Oversampling Based Designs

Stratix IV GX SI board: 1 Channel Multi-PRBS design at OC-3 rate using oversampling and creation of recovered clock through GPLL

GXIV_SIBoard_1Ch_Multi_Prbs_155Mbps_Clock_Recovery.zip

AEQ and EyeQ

Stratix IV GX SI board: 6 Channels Multi-PRBS design (using socket oscillator) with AEQ and EyeQ enabled

GXIV_SIBoard_6Ch_Multi_Prbs_Socket_Oscillator_EyeQ_ADCE.zip

EyeQ

Stratix IV GX SI board : 6 Channels Multi Prbs design (using socket oscillator) with EyeQ

GXIV_SIBoard_6Ch_Multi_Prbs_Socket_Oscillator_EyeQ.zip

SoftCDR & LVDS_PHY

Stratix IV GX PCIe Board: 4Ch LVDS_PHY_SoftCDR Demo at 1.25Gbps per Channel

SIVGX_DevKit_LVDS_Phy_1250Mbps_SoftCDR_4Ch_SFP.zip

Aurora

Stratix IV GX SI board: Aurora demo Design : 1 lane at 2.5Gbps

GXIV_SI_Board_Aurora_1_Lane_2500Mbps.zip

SFI5.1

Stratix IV GX SI board: 17 Channel Multi Prbs at 3.125Gbps using SFI5.1

GXIV_SIBoard_17Ch_Multi_Prbs_3125Mbps_16bit_SFI51_Implementation.zip

XAUI

Stratix IV GX SI board: XAUI Demo Design

GXIV_SIBoard_XAUI_Demo.zip

Dynamic Reconfiguration

Stratix IV GX SI board: Dynamic Reconfigurable Demo Design from XAUI <=> DXAUI

GXIV_SIBoard_DXAUI_XAUI_Demo.zip

Stratix IV GX SI board: Dynamic Reconfigurable Demo Design from XAUI <=> GbE <=> GIG3

GXIV_SIBoard_XAUI_GbE_GIG3.zip

Stratix IV GX SI board: 1Ch Dynamic Reconfiguration (Multi Rate Sonet, GbE, GIG3, FC-4 w/ 4 Input Clocks)

GXIV_SIBoard_1Ch_Multirate_Sonet_GbE_FC4_4_input_clocks.zip

Stratix IV GX SI board: 2Ch Dynamic Reconfiguration (Multi Rate Sonet, GbE, GIG3, FC-4 w/ 4 Input Clocks)

GXIV_SIBoard_2Ch_Multirate_Sonet_GbE_FC4_4_input_clocks.zip

Synchronous

Stratix IV GX SI board: 20Gbps Synchronous Demo 4 Scrambled Lanes at 5Gbps w/ Simple Training and Deskew

GXIV_SIBoard_Synchronous_4_Channels_5Gbps.zip

Seriallite II

Stratix IV GX Devkit: Seriallite II Demo Design Using LVDS: 4 lanes at 1.25Gbps

GXIV_DevKit_SerialliteII_LVDS_4Ch_1250Mbps.zip

Stratix IV GX SI Board: Seriallite II Demo Design: - 4 lanes at 6.25Gbps using PMA Only Channels

GXIV_SIBoard_Seriallite_4_Lanes_6250Mbps_PMA_Only.zip

Stratix IV GX SI Board: Seriallite II Demo Design: - 4 lanes at 6.25Gbps (Onboard 312.5Mhz XO)

GXIV_SI_Board_Seriallite_4_Lanes_6250Mbps.zip

Stratix IV GX SI Board: Seriallite II Demo Design: - 4 lanes at 8.5Gbps with external 8b10b PCS (Onboard 425Mhz XO)

GXIV_SI_Board_Seriallite_4_Lanes_8500Mbps.zip

Stratix IV GX SI board: Seriallite II Demo Design - 4 lanes at 8.5Gbps with internal 8b10b (Onboard 425 Mhz XO)

GXIV_SIBoard_Seriallite_4_Lanes_8500Mpbs.qar

(Note: The link above is only the Quartus II archive, for documentation please see the above 6.25Gbps design.)

SuperLite V2

Stratix IV GX SI board: Superlite V2 demo Design: 2 lanes at 4Gbps with Avalon ST Transmit Interface

GXIV_SIBoard_Superlite_v2_2_Lanes_4000Mbps_Avalon_ST.zip

SuperLite

Stratix IV GX SI Board: SuperLite Demo Design: 6 lanes at 6.25Gbps using embedded PCS in ALTGX

GXIV_SIBoard_Superlite_6_Lanes_6250Mbps_PCS.zip

Stratix IV GX SI Board: SuperLite Demo Design: 2 lanes at 4Gbps using embedded PCS in ALTGX

GXIV_SIBoard_Superlite_2_Lanes_4000Mbps.zip

Stratix IV GX SI Board: SuperLite Demo Design: 2 lanes at 6.25Gbps using PMA only channels or mixed mode

GXIV_SIBoard_Superlite_2_Lanes_6250Mbps_PMA_and_MIX.zip

Stratix IV GX SI Board: SuperLite Demo Design: 4 lanes at 8.5Gbps (Onboard 450Mhz XO)

GXIV_SIBoard_Superlite_4_Lanes_8500Mbps.zip