High-Speed Transceiver Demo Designs - Intel® Arria® 10 Series

High-Speed Transceiver Demo Designs - Intel® Arria® 10 Series

High-Speed Transceiver Demo Designs - Intel® Arria® 10 Series

For a list of Intel® Stratix® 10 GX High-Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Stratix-10-GX-Series/ta-p/735749.
For a list of Intel® Stratix® 10 TX High-Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Stratix-10-TX-Series/ta-p/735133.
Here is a list of Intel Agilex® FPGA I-Series (F-Tile) High-Speed Transceiver Demo Designs: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Agilex-I-Series-F-Tile/...
Here is a list of Intel Agilex® FPGA F-Series (E-tile) High-Speed Transceiver Demo Designs: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Agilex-Series/ta-p/1226...
For a list of V-Series (SVGX, AVGT, AVGX, and CVGX) High-Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-V-Series-StratixV-ArriaV-and/ta-p/735783.
For a list of IV-series (SIVGX) High-Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-IV-series-StratixIV-GX/ta-p/735787.

Index

1. Script with useful procedures for use in the system console

2. Superlite II V4 (with/without KRFEC)

3. PRBS Test designs with Transceiver Toolkit Support and ADME

4. Superlite II Synchronous

5. Link Tuning Test designs

6. Seriallite II with KR-FEC

7. Superlite II Video

8. Superlite V3

9. Superlite V2

10. Backplane Test designs with optional KR FEC + Transceiver Toolkit Support + ADME

11. Superlite II with KR-FEC at 25.8 Gbps

13. Seriallite II

14. Dynamic Reconfiguration

15. Ultralite II E Asynchronous (Enhanced)

16. Ultralite II Asynchronous

17. Transceiver Toolkit Designs

18. Ultralite

19. Oversampling

20. Ultralite II Synchronous

1. Script with useful procedures for use in the system console

(05/03/2018) This script is the most up-to-date version and replaces the ttk_helper.tcl script found in the projects below, it also contains an automatic AC gain optimization algorithm
- Ttk_helper.tcl V9.3 (05/03/2018)

2. Superlite II V4 (with/without KRFEC)

New (03/12/2021) Arria10 GX SI Board: Superlite II V4 with KRFEC Design using 4 lanes at 10.3125 Gbps routed to QSFP+ module (V4 uses simplified clocking and automatic lane identification)
- a10-siboard-superliteii-v4-krfec-4-lanes-10gbps-qsfp+.zip (21.3 B170)

Recently Updated (04/03/2021) Arria10 GX SI Board: Superlite II V4 Design using 4 lanes at 10.3125 Gbps routed to QSFP+ module (V4 uses simplified clocking and automatic lane identification)
- A10GX-SIBoard-SuperliteII-V4-4-lanes-10Gbps-QSFP+.zip (20.4 B72)

3. PRBS Test designs with Transceiver Toolkit Support and ADME

Recently Updated (20/04/2021) Arria10 GX PCIe Development Kit (Production): Multi Prbs Demo design using 4 lanes at 12.5 Gbps connected to FMC-A using FPLL (incl. TTK functionality and ODI capture and display functions running on the embedded processor)
- Arria10-Devkit-4Ch-Multi-Prbs-Native-Phy-12G5-FMC.zip (20.4 B72)

(08/12/2015) Arria10 GX SI Board (ES3): Multi Prbs Demo design using 4 lanes at 10.3125 Gbps with one lane connected to the SFP+ module (incl. TTK functionality and ODI capture and display functions running on the embedded processor)
- Arria10_SIBoard_4Ch_Multi_Prbs_Native_PHY_SFP.zip (15.1 B185)

(24/12/2014) Arria10 GX SI Board: Multi Prbs Demo design using 10 lanes at 10.0 Gbps using ODI workaround and auto sweep for optimum PMA settings using one reference clock only
- Arria10_SIBoard_10Ch_Multi_Prbs_Native_Phy_with_TTK_support_and_ODI_one_refclock.zip (14.0A10s B578 0.03)

(24/12/2014) Arria10 GX SI Board: Multi Prbs Demo design using 4 lanes at 10.0 Gbps using ODI workaround and auto sweep for optimum PMA settings using one reference clock only
- Arria10_SIBoard_4Ch_Multi_Prbs_Native_Phy_with_TTK_support_and_ODI_one_refclock.zip(14.0A10s B578 0.03)

(28/11/2014) Arria10 GX SI Board: Multi Prbs Demo design using 4 lanes at 10.3125 Gbps using ODI workaround and auto sweep for optimum PMA settings
- Arria10_SIBoard_4Ch_Multi_Prbs_Native_Phy_with_TTK_support_and_ODI.zip (14.0A10s B578 0.03)

(24/11/2014) Arria10 GX PCIe Development Kit: Multi Prbs Demo design using 4 lanes at 10.3125 Gbps using ODI workaround and auto sweep for optimum PMA settings
- Arria10_Devkit_4Ch_Multi_Prbs_Native_Phy_with_TTK_support_and_ODI.zip (14.0A10s B578 0.03)

(18/11/2014) Arria10 GX PCIe Development Kit: Multi Prbs Demo design using 12 lanes at 10.3125 Gbps routed to FMC connector A (non-bonded)
- Arria10_Devkit_12Ch_Multi_Prbs_Native_Phy_with_TTK_support_not_bonded.zip (14.0A10s B578 0.03)

(14/11/2014) Arria10 GX PCIe Development Kit: Multi Prbs Demo design using 4 lanes at 10.3125 Gbps routed to FMC connector A
- Arria10_Devkit_4Ch_Multi_Prbs_Native_Phy_with_TTK_support.zip (14.0A10s B578 0.03)

4. Superlite II Synchronous

(20/04/2017) Arria10 GX SI Board: Superlite II Synchronous Design using 4 lanes at 8 Gbps all clocked from one 100 Mhz clock (incl. TTK functionality and ODI capture and display functions running on the embedded processor)
- A10GX_SIBoard_SuperliteII_Synchronous_4_lanes_8Gbps.zip (16.1.2 B203)

5. Link Tuning Test designs

(24/11/2016) Arria10 GX SI Board (Production): 4 Channel Link Tuning Test design (12.5 Gbps per lane) using 3 methods : ODI workaround, PMA sweep, and automatic AC gain optimization (Backplane and chip-to-chip)
- Arria10_SIBoard_4Ch_Multi_Prbs_with_ODI_Workaround.zip (16.1 B196)

6. Seriallite II with KR-FEC

Recently Updated (04/03/2021) Arria10 GX PCIe Devkit (Production) : Seriallite II with FREE KR-FEC demo design using 4 lanes at 12.5 Gbps (incl. TTK functionality and embedded ODI)
- Arria10-Devkit-Seriallite-4-Lanes-12-5Gbps-soft8b10b-KRFEC.zip (20.4 B72)

7. Superlite II Video

(01/03/2016) Arria10 GX SI Board (ES3)): Superlite II Video demo design transporting transparently Video and Aux Data across a 10.3 Gbps link
- A10GX_SIBoard_SuperliteII_Video_1_Lane.zip (15.1.2 B193)

8. Superlite V3

(11/02/2016) Arria10 GX PCIe Development Kit (ES2): Superlite V3 demo design with 1 lane at 2.5 Gbps (V3 offers handshaking and Flow Control (ON/XOFF)
- A10GX_Devkit_Superlite_V3_1_lane_2500Mbps.zip (15.1.2 B192)

(02/03/2018) Arria10 GX SI Board (Prod): Superlite V3 demo design with 1 lane at 2.5 Gbps (V3 offers handshaking and Flow Control (ON/XOFF)
- Arria10_SIBoard_Superlite_V3_1_lane_2500Mbps.zip (17.1.1 B273)

9. Superlite V2

NEW (04/08/2021) Arria10 GX PCIe Development Kit (Prod): Superlite V2 demo design with 4 lanes at 12.5 Gbps using soft 8B10B (incl. TTK functionality and ODI capture and display functions running on the embedded processor)
- A10-Devkit-Superlite-V2-4-Lanes-soft8b10b-12.5Gbps-Prod.zip (20.4 B72)

(05/02/2016) Arria10 GX PCIe Development Kit (ES2): Superlite V2 demo design with 1 lane at 2.5 Gbps (incl. TTK functionality and ODI capture and display functions running on the embedded processor)
- A10GX_Devkit_Superlite_V2_1_lane_2500Mbps.zip (15.1.2 B192)

(Updated) (03/12/2019) Arria10 GX PCIe Development Kit (Production): Superlite V2 demo design with 4 lanes at 2.5 Gbps (incl. TTK functionality and ODI capture and display functions running on the embedded processor)
- A10GX_Devkit_Superlite_V2_4_lanes_2500Mbps.zip (19.3 B222)

10. Backplane Test designs with optional KR FEC + Transceiver Toolkit Support + ADME

(07/01/2016) Arria10 GX SI Board (ES3): Multi PRBS Backplane demo design with optional KR-FEC (4 lanes at 16 Gbps) (the design uses dynamic reconfiguration of the channel to switch between KR-FEC mode and normal mode)
- Arria10_SIBoard_4Ch_Multi_Prbs_ES3_16Gbps_with_optional_KRFEC.zip (15.1.1 B189)

11. Superlite II with KR-FEC at 25.8 Gbps

(13/11/2015) Arria10 GX SI Board : Superlite II with FREE KR-FEC demo design using 4 GT lanes at 25.781 Gbps (incl. TTK functionality and ODI capture and display functions running on the embedded processor)
- A10GX_SIBoard_SuperliteII_with_KRFEC_4_lanes_25.8Gbps.zip (15.1 B185)

12. Seriallite II

Recently Updated (03/03/2021) Arria10 GX PCIe Development Kit (Production): Seriallite II demo design with 4 lanes at 10 Gbps (incl. TTK functionality and embedded ODI)
- Arria10-Devkit-Seriallite-4-Lanes-10Gbps.zip (20.4 B72)

(16/09/2015) Arria10 GX PCIe Development Kit (ES2): Seriallite II demo design with 4 lanes at 12.5 Gbps using 8b10b soft PCS (incl. TTK functionality and ODI capture and display functions running on the embedded processor)
- Arria10_Devkit_Seriallite_4_Lanes_12_5Gbps_soft8b10b_ES2.zip (15.0.2 B153)

(14/01/2015) Arria10 GX SI Board: Seriallite II demo design with 4 lanes at 10 Gbps (incl. TTK functionality)
- Arria10_SIBoard_Seriallite_4_Lanes_10Gbps_14_1.zip (14.1A10s B652)

14. Dynamic Reconfiguration

(23/06/2016) Arria10 GX SI Board (ES3): 4 Ch Dynamic Reconfiguration Demo Design Using Data rate reconfiguration and TX PLL clock switching. (incl. TTK functionality)
- Arria10_SIBoard_4Ch_TXPLL_and_datarate_reconfiguration.zip (16.0.1 B218)

(06/07/2015) Arria10 GX PCIe Development Kit (ES2): 4 Ch Dynamic Reconfiguration Demo Design Using Fast Reconfig , using 3 datarates (DP Testcase) with bonding (incl. TTK functionality)
- Arria10_Devkit_4Ch_DPRIO_3_datarates_DP_testcase_fast_reconfig.zip (15.0.1 B150)

(04/05/2015) Arria10 GX SI Board : 4 Ch Dynamic Reconfiguration Demo Design Using Fast Reconfig using 3 datarates (DP Testcase) with bonding (incl. TTK functionality)
- Arria10_SIBoard_4Ch_DPRIO_3_datarates_DP_testcase_fast_reconfig.zip (15.0.1 B147)

(03/04/2015) Arria10 GX PCIe Development Kit : 4 Ch Dynamic Reconfiguration Demo Design Using Embedded Streamer and Dynamic fPLL Programming, using 3 datarates (DP Testcase) with bonding (incl. TTK functionality)
- Arria10_Devkit_4Ch_DPRIO_3_datarates_DP_testcase.zip (15.0 CB B139)

15. Ultralite II E Asynchronous (Enhanced)

(14/08/2020) Arria10 GX PCIe Development Kit (Production) : Ultralite II E Asynchronous demo design to transport 40 Gbps data using 4 lanes at 10 Gbps (incl. TTK functionality and EyeQ) this variant is using the Rx block sync, scrambler and descrambler from the Enhanced PCS
- Arria10_Devkit_UltraliteII_E_Asynchronous_4_Lanes_10Gbps_Prod.zip (20.2 B50)

16. Ultralite II Asynchronous

(12/05/2015) Arria10 GX PCIe Development Kit (ES2) : Ultralite II Asynchronous demo design to transport 50 Gbps data using 4 lanes at 12.5 Gbps (incl. TTK functionality and EyeQ)
- Arria10_Devkit_UltraliteII_Asynchronous_4_Lanes_12500Mbps_ES2.zip (15.0.1 B147)

(25/02/2015) Arria10 GX PCIe Development Kit : Ultralite II Asynchronous demo design to transport 40 Gbps data using 4 lanes at 10 Gbps (incl. TTK functionality)
- Arria10_Devkit_UltraliteII_Asynchronous_4_Lanes_10Gbps.zip

17. Transceiver Toolkit Designs

(23/11/2016) Arria10 GX SI Board Rev E4(Production): 24 Channel Transceiver Toolkit design at 12.5 & 10.3125 Gbps (QSFP+) using 3 Native PHY's (includes tcl file with multiple useful procedures)
- http://fpgawiki.intel.com/wiki/File:Arria10_SIBoard_24Ch_TTK.zip (16.1 B196)

(27/01/2017) Arria10 GX PCIe Development Kit (Production): : 12 Channel Transceiver Toolkit design at 12.5 Gbps routed to FMC connector A (non-bonded) (includes tcl file listed on top of the page)
- Arria10_Devkit_12Ch_TTK.zip (16.1.1 B200)

(27/01/2017) Arria10 GX PCIe Development Kit (Production): : 4 Channel Transceiver Toolkit design at 12.5 Gbps routed to FMC connector A (non-bonded) (includes tcl file listed on top of the page)
- Arria10_Devkit_4Ch_TTK.zip (16.1.1 B200)

18. Ultralite

(03/07/2015) Arria10 GX PCIe Development Kit (ES2): Ultralite Synchronous demo design (80 ns Tx to Rx latency) to transport 96 Gbps data using 12 lanes at 10 Gbps (incl. TTK functionality)
- Arria10_Devkit_Ultralite_Synchronous_12_lanes.zip (15.0.1 B150)

(28/11/2014) Arria10 GX SI Board: Ultralite Synchronous demo design (80 ns Tx to Rx latency) to transport 32 Gbps data using 4 lanes at 10 Gbps
- A10GX_SIBoard_Ultralite_Synchronous_4_Lanes.zip (14.0A10s B578 0.03)

Arria10 GX SI Board: Ultralite Synchronous demo design (sub 100 ns Tx to Rx latency) to transport 100 Gbps data using 12 lanes at 10+ Gbps (not ported to board)
- A10GX_SIBoard_Ultralite_Synchronous_12_Lanes.zip

19. Oversampling

(01/12/2017) Arria10 GX SI Board : 11x Oversampling Design using 4 lanes at 150 Mbps using PRBS
- Arria10_SIBoard_4Ch_Prbs_Oversampling_x11.zip(16.1.2 B203)

20. Ultralite II Synchronous

Arria10 GX SI Board: Ultralite II Synchronous demo design to transport 100-120 Gbps data using 10 lanes at 10-12.5 Gbps (not ported to board)
- A10GX_SIBoard_UltraliteII_Synchronous_10_Lanes.zip

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