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High Speed Transceiver Demo Designs - Arria 10 Series

High Speed Transceiver Demo Designs - Arria 10 Series

 

Index

1. Script with useful procedures for use in system console

2. Superlite II V4 (with/without KRFEC)

3. PRBS Test designs with Transceiver Toolkit Support and ADME

4. Superlite II Synchronous 

5. Link Tuning Test designs

6. Seriallite II with KR-FEC 

7. Superlite II Video

8. Superlite V3

9. Superlite V2

10. Backplane Test designs with optional KR FEC + Transceiver Toolkit Support + ADME

11. Superlite II with KR-FEC at 25.8 Gbps  

13. Seriallite II

14. Dynamic Reconfiguration

15. Ultralite II E Asynchronous (Enhanced)

16. Ultralite II Asynchronous

17. Transceiver Toolkit Designs

18. Ultralite

19. Oversampling 

20. Ultralite II Synchronous

 

 

1. Script with useful procedures for use in system console

 

  • (05/03/2018) This script is the most up to date version and replaces the ttk_helper.tcl script found in the projects below, it also contains an automatic AC gain optimization algorithm

 

2. Superlite II V4 (with/without KRFEC)

 

 

  • Recently Updated  (04/03/2021) Arria10 GX SI Board : Superlite II V4 Design using 4 lanes at 10.3125 Gbps routed to QSFP+ module (V4 uses simplified clocking and automatic lane identification) 

 

3. PRBS Test designs with Transceiver Toolkit Support and ADME

 

  •  Recently Updated (20/04/2021) Arria10 GX PCIe Development Kit (Production): Multi Prbs Demo design using 4 lanes at 12.5 Gbps connected to FMC-A using FPLL (incl. TTK functionality and ODI capture and display functions running on the embedded processor)

 

  • (08/12/2015) Arria10 GX SI Board (ES3): Multi Prbs Demo design using 4 lanes at 10.3125 Gbps with one lane connected to the SFP+ module (incl. TTK functionality and ODI capture and display functions running on the embedded processor)

 

 

 

 

 

 

 

  •  

4. Superlite II Synchronous

 

  • (20/04/2017) Arria10 GX SI Board : Superlite II Synchronous Design using 4 lanes at 8 Gbps all clocked from one 100 Mhz clock (incl. TTK functionality and ODI capture and display functions running on the embedded processor)

 

5. Link Tuning Test designs

 

  • (24/11/2016) Arria10 GX SI Board (Production): 4 Channel Link Tuning Test design (12.5 Gbps per lane) using 3 methods : ODI workaround, PMA sweep and automatic AC gain optimization (Backplane and chip-to-chip)

 

6. Seriallite II with KR-FEC

 

 

 

7. Superlite II Video

 

8. Superlite V3

 

 

 

9. Superlite V2

 

  • NEW (04/08/2021) Arria10 GX PCIe Development Kit (Prod): Superlite V2 demo design with 4 lanes at 12.5 Gbps using soft 8B10B (incl. TTK functionality and ODI capture and display functions running on the embedded processor)

 

  • (05/02/2016) Arria10 GX PCIe Development Kit (ES2): Superlite V2 demo design with 1 lane at 2.5 Gbps (incl. TTK functionality and ODI capture and display functions running on the embedded processor)

 

  • (Updated) (03/12/2019) Arria10 GX PCIe Development Kit (Production): Superlite V2 demo design with 4 lanes at 2.5 Gbps (incl. TTK functionality and ODI capture and display functions running on the embedded processor)

 

10. Backplane Test designs with optional KR FEC + Transceiver Toolkit Support + ADME

 

 

 

11. Superlite II with KR-FEC at 25.8 Gbps

 

  • (13/11/2015) Arria10 GX SI Board : Superlite II with FREE KR-FEC demo design using 4 GT lanes at 25.781 Gbps (incl. TTK functionality and ODI capture and display functions running on the embedded processor)

 

12. Seriallite II

 

  • Recently Updated (03/03/2021) Arria10 GX PCIe Development Kit (Production): Seriallite II demo design with 4 lanes at 10 Gbps (incl. TTK functionality and embedded ODI)

 

  • (16/09/2015) Arria10 GX PCIe Development Kit (ES2): Seriallite II demo design with 4 lanes at 12.5 Gbps using 8b10b soft PCS (incl. TTK functionality and ODI capture and display functions running on the embedded processor)

 

 

14. Dynamic Reconfiguration

 

 

 

 

  • (03/04/2015) Arria10 GX PCIe Development Kit : 4 Ch Dynamic Reconfiguration Demo Design Using Embedded Streamer and Dynamic fPLL Programming, using 3 datarates (DP Testcase) with bonding (incl. TTK functionality) 

 

15. Ultralite II E Asynchronous (Enhanced)

 

  • (14/08/2020) Arria10 GX PCIe Development Kit (Production) : Ultralite II E Asynchronous demo design to transport 40 Gbps data using 4 lanes at 10 Gbps (incl. TTK functionality and EyeQ) this variant is using the Rx block sync, scrambler and descrambler from the Enhanced PCS

 

16. Ultralite II Asynchronous

 

 

 

17. Transceiver Toolkit Designs

 

 

  • (27/01/2017) Arria10 GX PCIe Development Kit (Production): : 12 Channel Transceiver Toolkit design at 12.5 Gbps routed to FMC connector A (non-bonded) (includes tcl file listed on top of the page)

 

  • (27/01/2017) Arria10 GX PCIe Development Kit (Production): : 4 Channel Transceiver Toolkit design at 12.5 Gbps routed to FMC connector A (non-bonded) (includes tcl file listed on top of the page)

 

18. Ultralite

 

  • (03/07/2015) Arria10 GX PCIe Development Kit (ES2): Ultralite Synchronous demo design (80 ns Tx to Rx latency) to transport 96 Gbps data using 12 lanes at 10 Gbps (incl. TTK functionality)

 

 

 

19. Oversampling

 

20. Ultralite II Synchronous

 

Version history
Revision #:
22 of 22
Last update:
‎12-07-2021 04:15 AM
Updated by:
 
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