High-Speed Transceiver Demo Designs V-Series (StratixV, ArriaV and CycloneV)

High-Speed Transceiver Demo Designs V-Series (StratixV, ArriaV and CycloneV)

For a list of Stratix 10 GX High-Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Stratix-10-GX-Series/ta-p/735749
For a list of Stratix 10 TX High-Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Stratix-10-TX-Series/ta-p/735133
For a list of Arria 10 High Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-Arria-10-Series/ta-p/735131
For a list of IV-series (SIVGX) High-Speed Transceiver Demo Designs, go here: https://community.intel.com/t5/FPGA-Wiki/High-Speed-Transceiver-Demo-Designs-IV-series-StratixIV-GX/ta-p/735787

Cyclone V GX

Seriallite II

(07/12/2015)Cyclone V GX Devkit: Seriallite II Demo Design Using 15.1 Megacore, 4 Lanes at 2.5Gbps

CVGX_Devkit_Seriallite_4_Lanes_2500Mbps_Megacore.zip (15.1 B185)

Stratix V GT

Fixed Rate (PRBS)

Stratix V GT SI Board: 4 Channel Multi-PRBS at 25 Gbps with minimal TX skew

GTV_SI_Board_4Ch_Multi_Low_Latency_skew_test.zip

Stratix V GT SI Board: 4 Channel Multi-PRBS at 25 Gbps

GTV_SI_Board_4Ch_Multi_Prbs_Low_Latency_25Gbps.zip

Stratix V GX

Backplane with Temperature Tracking IP

(26/11/2015) Stratix V GX SI Board: 4 Channel 10.3125 Gbps Backplane demo design with Temperature Tracking IP

GXV_SI_Board_4Ch_Multi_Prbs_Native_Phy_Temp_Tracking_Backplane.zip (15.0.2 B153)

Ultralite II

Stratix V GX SI Board: Ultralite II Synchronous demo design to transport 100-120 Gbps data using 10 lanes at 10-12.5 Gbps

GXV_SIBoard_UltraliteII_Synchronous_10_Lanes.zip

Stratix V GX SI Board: Ultralite II Synchronous demo design to transport 50-60 Gbps data using 5 lanes at 10-12.5 Gbps

GXV_SIBoard_UltraliteII_Synchronous_5_Lanes.zip

Oversampling

Stratix V GX SI Board: OC3 Oversampling design (5x) with recreation of recovered clock using fPLL and PI controller

GXV_SIBoard_1Ch_Multi_Prbs_155Mbps_Clock_Recovery.zip

DXAUI

Stratix V GX SI Board: DXAUI demo design using Native PHY and external DXAUI PCS

GXV_SIBoard_DXAUI_Demo.zip

Ultralite

Stratix V GX SI Board: Ultralite Synchronous demo design (sub 100 ns Tx to Rx latency) to transport 100 Gbps data using 12 lanes at 10+ Gbps

GXV_SIBoard_Ultralite_Synchronous_12_Lanes.zip

EyeQ, BERB and DFE

Stratix V GX SI Board: 4 Ch Multi-PRBS demo design illustrating EyeQ and BERB in 2D mode + One Time DFE + DVD and Slew Rate Control running at 14.1 Gbps

GXV_SI_Board_4Ch_Multi_Prbs_Native_Phy_EyeQ_BERB_2D_DFE_DCD_Slewrate_14Gbps.zip

Stratix V GX SI Board: 4 Ch Multi-PRBS demo design illustrating EyeQ and Berb in 2D mode + One Time DFE + DCD and Slew Rate Control

GXV_SI_Board_4Ch_Multi_Prbs_Native_Phy_EyeQ_BERB_2D_DFE_DCD_Slewrate_14Gbps.zip

Superlite II

Stratix V GX SI Board: Superlite II V2 Packet Mode Demo Design: 11 Lanes at 12.5 Gbps

GXV_SIBoard_SuperliteII_V2_Packet_Mode_11_Lanes.zip

Stratix V GX SI Board: Superlite II V2 Streaming Mode Demo Design: 11 lanes at 12.5 Gbps

GXV_SIBoard_SuperliteII_V2_11_Lanes.zip

Stratix V GX SI Board: Superlite II demo design: 5 Lanes at 11.3 Gbps

GXV_SI_Board_Superlite_II_5_Lanes_11Gbps.zip

Stratix V GX SI Board: Superlite II Demo Design: 10 Lanes at 11.3 Gbps

GXV_SI_Board_Superlite_II_10_Lanes_11Gbps.zip

Dynamic Reconfiguration

Stratix V GX SI Board: 1 Ch Dynamic Reconfiguration Demo Design Using Direct Mode 3 to Reconfigure ATX PLL

StratixV_SIBoard_1Ch_Multi_Prbs_DPRIO_2_SW_13_0_Direct_Mode_3_1_Refclk.zip

Stratix V GX SI Board: 4 Ch Dynamic Reconfiguration Demo Design Using Dynamic RefClock Switching and Dynamic fPLL Programming w/ independent Tx and Rx Operation Bonded Tx (DP++ testcase using MIF mode 1); 5.4, 2.7 and 1.62 Gbps Data Rates for DisplayPort, contiguous 1 Gbps .. 6 Gbps data rates for HDMI

StratixV_SIBoard_4Ch_DPRIO_DPplusplus_TestCase_13_1_bonded.zip

Stratix V GX SI Board: 4 Ch Dynamic Reconfiguration Demo Design Using Dynamic RefClock Switching w/ independent Tx and Rx Operation Bonded Tx (DP++ testcase using MIF mode 1)

StratixV_SIBoard_4Ch_DP_TestCase_4_datarates_12_1_Native_Phy_V2_bonded.zip

Stratix V GX SI Board: 4 Ch Dynamic Reconfiguration Demo Design Using Dynamic RefClock Switching with Independent Tx and Rx Operation (DP++ testcase using MIF mode 1)

GXV_SI_Board_4Ch_DPRIO_4_datarates_DPplus_Testcase.zip

Stratix V GX SI Board: 4 Ch Dynamic Reconfiguration Demo Design Using Dynamic RefClock Switching with Independent Tx and Rx Operation (Displayport Testcase) (Using MIF mode 0)

GXV_SI_Board_4Ch_DPRIO_3_datarates_DP_Testcase.zip

Stratix V GX SI Board: 1 Ch Dynamic Reconfiguration Demo Design Using MIF Streamer Mode 0 (reconfigure between 10.3125 Gbps and 8.5 Gbps) using LC PLL and Native PHY

GXV_SI_Board_1Ch_DPRIO_2_Datarates_MIF_Streaming.zip

Stratix V GX SI Board: 4 Ch Dynamic Reconfiguration Demo Design Using Dynamic RefClock Switching

GXV_SI_Board_4Ch_DPRIO_2_RefClock.zip

Seriallite II

Stratix V GX SI Board: Seriallite II Demo Design Using 13.0 Megacore, 4 Lanes at 2.5Gbps

GXV_SI_Board_Seriallite_4_Lanes_2500Mbps_Megacore.zip

Stratix V GX SI Board: Seriallite II Demo Design Using 12.1 Megacore, 4 lanes at 10.3125Gbps

GXV_SI_Board_Seriallite_4_Lanes_10Gbps_Megacore.zip

Stratix V GX SI Board: Seriallite II Demo Design 4 lanes at 10.3125Gbps or 16x External Reference Clock Frequency (Not recommended-for new designs see Megacore design)

GXV_SI_Board_Seriallite_4_Lanes_10Gbps.zip

Stratix V GX Development Kit: Seriallite II Demo Design: 4 Lanes at 6.25Gbps

(Not recommended-for new designs see Megacore design)

GXV_Devkit_Seriallite_4_Lanes_6250Mbps.zip

Fixed Rate (PRBS)

Stratix V GX SI Board: 10 Channel Multi-PRBS at 10.3125Gbps or 16x External Reference Clock Frequency

GXV_SI_Board_10Ch_Multi_Prbs_Low_Latency.zip

Stratix V GX SI Board: 1 Channel XFP Multi-PRBS at 10.3125Gbps w/ Reverse Parallel Loopback

GXV_SI_Board_1Ch_Multi_Low_Latency_XFP.zip

Stratix V GX SI Board: 1 Channel XFP Multi-PRBS at 10.3125Gbps w/ reverse parallel loopback and XFP RefClock

GXV_SI_Board_1Ch_Multi_Low_Latency_XFP_with_refclk_XFP.zip

Stratix V GX SI Board: 1 Channel SMA Multi-PRBS at 10.3125Gbps w/ Reverse Parallel Loopback

GXV_SI_Board_1Ch_Multi_Low_Latency_SMA.zip

Stratix V GX SI Board: 4 Channel Multi-PRBS at 10.3125Gbps or 16x External Reference Clock Frequency

GXV_SI_Board_4Ch_Multi_Low_Latency.zip

Stratix V GX Development Kit: 4 Channel Multi-PRBS at 6.25Gbps (Onboard 156.25Mhz Oscillator)

GXV_Devkit_4Ch_Multi_Prbs_6250Mbps.zip

ArriaV GX

Oversampling

(05/01/2016) ArriaV GX Starterkit : 4 Channels Multi Prbs at 500 Mbps using 5x oversampling with 10000 ppm difference between Tx and Rx

AV_Starter_Kit_4Ch_Multi_Prbs_5x_oversampling_500Mbps.zip (15.1.1 B189)

fPLL as TxPLL

ArriaV GX Starterkit: 4 Channels Multi-PRBS at 3.125Gbps using fPLL as TxPLL

AV_Starter_Kit_4Ch_Multi_Prbs_fPLL_as_TxPLL.zip

Dynamic Reconfiguration

ArriaV GX Starterkit: 4 Ch Dynamic Reconfiguration demo Design with independent Tx and Rx operation and bonded Tx (DP testcase using MIF mode 1)

AV_Starter_Kit_4Ch_DP_TestCase_3_datarates_bonded.zip

Superlite

ArriaV GX Starterkit: Superlite Demo Design - 4 lanes at 3.125Gbps

AV_Starter_Kit_Superlite_4_Lanes_3125Mbps.zip

Fixed Rate (PRBS)

ArriaV GX Starterkit : 4 Channels Multi-PRBS at 3.125Gbps using the HSMC Connector

AV_Starter_Kit_4Ch_Multi_Prbs.zip