High Speed Transceiver Demo Designs - Intel Agilex® FPGA F-Series (E-tile)

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High Speed Transceiver Demo Designs - Intel Agilex® FPGA F-Series (E-tile)

High-Speed Transceiver Demo Designs - Intel Agilex® FPGA F-Series (E-Tile)

 

Index

  1. Multi-Prbs Generators and Checkers
  2. Script with useful procedures for use in the system console for Agilex (E-Tile)
  3. Library of C-functions for E-tile transceivers using AVMM Interface
  4. Superlite II V4 (no FEC)
  5. 100GbE
  6. Soft PRBS with/without RSFEC + Dynamic Reconfiguration Test Designs

 

1. Multi-Prbs Generators and Checkers

  • (28/04/2021) Collection of Multi-Prbs Generators and Verifiers used in various transceiver demo's with different bit widths: 32-bit, 64-bit, 128-bit, and 256-bit. Includes testbench as well. 

 

2. Script with useful procedures for use in the system console for Intel Agilex® FPGA (E-Tile)

 

3. Library of C-functions for E-tile transceivers using AVMM Interface

  • Functions for configuring PMA settings, adaptation, etc. (The same as from the Stratix 10 TX page) :

 

4. Superlite II V4 (no FEC)

 

 

 

5. 100GbE

 

6. Soft PRBS with/without RSFEC + Dynamic Reconfiguration Test Designs

  • (19/05/2021) Agilex PCIe Kit (ES Version): 2x 4 channel NRZ/PAM4 26 Gbps soft PRBS test design. Can be dynamically reconfigured to 10.3125 Gbps.

 

  • Updated (15/02/2022) Agilex PCIe Kit (ES Version): 2x 4 channel NRZ 28.3 Gbps soft PRBS with RSFEC in FRACTURED mode test design that can by dynamically reconfigured to :
    • NRZ/PAM4 RSFEC Fractured (528,514) (line rate is 25.78125 Gbps from 156.25 Mhz clock (x165) or any reconfigurable rate)              
    • NRZ/PAM4 RSFEC Fractured (544,514) (line rate is 26.5625 Gbps from 156.25 Mhz clock (x170) or any reconfigurable rate)   
    • PAM4 KPFEC Aggregate (544,514) with 2 physical lanes (line rate is 53.125 Gbps from 156.25 Mhz clock (x170x2) or any reconfigurable rate
    • NRZ PMA direct mode with 4 physical lanes (line rate is 25.78125 Gbps from 156.25 Mhz clock (x165) or any reconfigurable rate
    • PAM4 PMA direct mode with 2 physical lanes (line rate is 53.125 Gbps from 156.25 Mhz clock (x170x2) or any reconfigurable rate
    • NEW: Reconfigure individual lanes 1-3 from RSFEC to PMA direct (line rate is (tx_clk_divider (configurable)  x refclk frequency), and PMA direct to RSFEC fractured.
    • NEW: when all lanes are in PMA direct NRZ mode: reconfigure lane 0-3 to any reconfigurable datarate (line rate is (tx_clk_divider (configurable)  x refclk frequency)
    • Connected to QSFP-DD Modules + Adaptation Soft IP in each PHY, + LPM + PMA configuration supports + I2C, etc.
    • Agilex-PCIe-Kit-2x4Ch-qsfpdd-adapt-sip-rsfec-fract-to-kpfec-aggr-pma-direct.zip (21.4 B67)
Version history
Last update:
‎03-14-2023 10:39 AM
Updated by: