Error (170084): Can't route signal "modular_adc_0_adc_pll_clock_clk~input" to atom "daff1_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|primitive_instance"
AND
Error (171000): Can't fit design in device
THIS SHOWS WHEN I START ( FITTER ( PLACE & ROUTE) )......
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6 回复数
Hi,
Please check the '*.qar' available in below link, If in case it is required to upgrade, first upgrade it
https://forums.intel.com/s/createarticlepage?articleid=a3g0P0000005Rc9QAE&artTopicId=0TO0P000000MWKBWA4&action=view
You can also check the attached .qar upgraded in Q18.1 Lite.
Please let me know if you have any different concern.
Regards,
Vicky
