Intel® FPGA University Program
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I am having problems using a simulation clock in my testbenches.

CGood8
Beginner
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The .sv files compile in ModelSim but they do not compile in quartus prime.I have uploaded the tesbench in question in a .txt file and the error codes in produces in a separate .txt file

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RichardTanSY_Intel
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You may want to write the clocking block as

 

default clocking cb @(posedge Clock);

 

in line 43. I hope it helps.

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