Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
1184 Discussions

JTAG Bahvior is Different from EPCS4

Altera_Forum
Honored Contributor II
1,075 Views

Hi all, I have a DE1 board. I design a circuit, very simple circuit with one 8-bit counter. It has a PLL in it too. The PLL generates 50 MHz input clock and bring it down to 10 MHz. 

 

When I program DE1-Cyclone II with JTAG, it works fine. When I load the design into EPCS4, and recycle power, the circuit stops working? Any idea. I run sims, it works fine too. 

 

The PLL has a reset, but it does not matter in this case as I suspect the PLL is not working at all when power up from EPCS4. 

 

Thanks.
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
347 Views

Hi,  

 

1) Do you have a explicit reset in your counter ? 

 

2) Do you check you output configuration for epcs ? I mean there may be a problem with your epcs : program file or design. I suspect program file (.pof). 

 

3) Else...
0 Kudos
Altera_Forum
Honored Contributor II
347 Views

You are right. The pof file is corrupted. I am using Quartus II 9.1 SP2. It has a bug in generating pof file. Thanks. I have had this problem before, but almost forget about it now.

0 Kudos
Altera_Forum
Honored Contributor II
347 Views

Don't forget to add to mmtsuchi's reputation (http://www.alteraforum.com/forum/reputation.php?p=119793) ;-)

0 Kudos
Reply