Hello,I'm a rookie user of Quartus II suite and an entry-level VHDL developer. After creating a project in which I used an Altera IP megafunction (a shift register), the University Program VWF won't work again. It states: "Error: (vsim-3170) Could not find 'work.SIMPLEADDER_vlg_vec_tst'." I'm writing code in VHDL, but I noticed that every time I try running a RTL simulation in University Program VWF the EDA Tool Format Setting switches to Verilog HDL by itself, whereas I select VHDL prior to beginning the simulation. Does anybody have an idea about what is the problem? Consider that I was able to simulate without issues before creating and trying to simulate one project with an IP component. Thank you in advance.
Hi have the same issue.# vsim -c -do "PWM.do" # Start time: 13:23:20 on Jan 13,2015# ** Error: (vsim-3170) Could not find 'work.PWM_vlg_vec_tst'.# # Error loading design Error loading design # End time: 13:23:20 on Jan 13,2015, Elapsed time: 0:00:00# Errors: 1, Warnings: 0 Error.
Solved !!! We should define the top-level entity:a) Press "Ctrl+Shift+E" b) Go to General -> Top-Level entity -> click on browse file and select correct entity... That sould solve the problem. Best regards.
--- Quote Start --- Solved !!! We should define the top-level entity: a) Press "Ctrl+Shift+E" b) Go to General -> Top-Level entity -> click on browse file and select correct entity... That sould solve the problem. Best regards. --- Quote End --- It worked. Thank you! :) Nevertheless I don't remember changing the definition for the top-level entity; in fact when I opened the General options for the project the correct entity was already selected. It looks like the General settings of the project just needed to be opened (and OK button clicked). Weird...
exactly! had the same problem and i did defined my .vhd file as the top level entity (by right clicking) and when i opened settings it already was a top level entity but after pressing ok and simulating again it did work! stange... must be a bug or something