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library ieee;
use ieee.std_logic_1164.all;
entity dflipflop is
port( D,clk: in std_logic;
Q: out std_logic
);
end dflipflop;
architecture struct of dflipflop is
component dLatch is
port( clk,D : in std_logic;
Q : out std_logic
);
end component;
signal Qm : std_logic;
begin
hex_1 : dLatch port map(D=>D, clk=>S, Q=>Q);
end struct;
library ieee;
use ieee.std_logic_1164.all;
entity dLatch is
port( clk,D : in std_logic;
Q : out std_logic
);
end dLatch;
architecture struct of dLatch is
signal S,R,R_g, S_g, Qa, Qb : std_logic;
attribute keep : boolean;
attribute keep of R_g, S_g, Qa, Qb : signal is true;
begin
S <= D;
R <= not(D);
R_g <= R nand clk;
S_g <= S nand clk;
Qa <= S_g nand Qb;
Qb <= R_g nand Qa;
Q <= Qa;
end struct;
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UPDATED: first entity has wrong declarations
library ieee;
use ieee.std_logic_1164.all;
entity dflipflop is
port( D,clk: in std_logic;
Q: out std_logic
);
end dflipflop;
architecture struct of dflipflop is
component dLatch is
port( clk,D : in std_logic;
Q : out std_logic
);
end component;
signal Qm : std_logic;
begin
master : dLatch port map(D=>D, clk=>not(clk), Q=>Qm);
slave : dLatch port map(D=>Qm, clk=>clk, Q=>Q);
end struct;
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Can you post the text of the error message? It's hard to see an issue without knowing what the issue is that's reported.
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I had figured it out. dLatch is a primitive word which was causing the error
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Hi,
It's glad that you found the root cause.
Thanks
Best regards,
KhaiY
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