2DFF synchronizer output was determined to be a clock by timing analyzer

[PonPon]

Hello everyone, I'm the newbie in FPGA.

I want to design a frequency counter, so the design will involved some CDC problem.

Therefore, I used FIFO(I use the quartus fifo ip) and 2DFF synchronizer in my design.

Below is my RTL picture:

More information for the 2DFF synchronizer :

OK, here comes the problem.

When I use Timing Analyzer to deal with the timing constraints,

the system always give me a warning like this:

Warning (332060): Node: synchronizer:S1|DFF_SYNC:D2|Q was determined to be a clock but was found without an associated clock assignment.

Info (13166): Register FIFO_2:FIFO2|dcfifo:dcfifo_component|dcfifo_m9q1:auto_generated|altsyncram_b1b1:fifo_ram|ram_block11a10~porta_datain_reg3 is being clocked by synchronizer:S1|DFF_SYNC:D2|Q

The Node: synchronizer:S1|DFF_SYNC:D2|Q I think it shouldn't be a clock signal,

it's just a signal that I want to synchronize to the clk domain.

I used to have a previous sdc file, and in the previous sdc file,this problem didn't exist,

but after I restart a new sdc file, and do the same constraints (maybe, I  don't realy sure about this ) as the previos one, this warning shows up.

Can somebody tell me what's wrong with it? And how to fix it? Thx.

[PonPon]

I also gives you my sdc file:

## Generated SDC file "R_fcnt_test.out.sdc"

## Copyright (C) 2018 Intel Corporation. All rights reserved.
## Your use of Intel Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Intel Program License
## Subscription Agreement, the Intel Quartus Prime License Agreement,
## the Intel FPGA IP License Agreement, or other applicable license
## agreement, including, without limitation, that your use is for
## the sole purpose of programming logic devices manufactured by
## Intel and sold by Intel or its authorized distributors. Please
## refer to the applicable agreement for further details.

## VENDOR "Altera"
## PROGRAM "Quartus Prime"
## VERSION "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition"

## DATE "Mon Sep 30 20:02:41 2024"

##
## DEVICE "5CSEBA6U23I7"
##

#**************************************************************
# Time Information
#**************************************************************

set_time_format -unit ns -decimal_places 3

#**************************************************************
# Create Clock
#**************************************************************

create_clock -name {clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk}]
create_clock -name {fin} -period 12500.000 -waveform { 0.000 6250.000 } [get_ports {fin}]
create_clock -name {altera_tck} -period 1000.000 -waveform { 0.000 500.000 } [get_ports {altera_reserved_tck}]
create_clock -name {altera_tdo} -period 10.000 -waveform { 0.000 5.000 } [get_ports {altera_reserved_tdo}]

#**************************************************************
# Create Generated Clock
#**************************************************************

create_generated_clock -name {gate} -source [get_ports {clk}] -divide_by 50000 -master_clock {clk} [get_keepers {gate:G1|gate}]
create_generated_clock -name {fin_div2} -source [get_ports {fin}] -divide_by 2 -master_clock {fin} [get_pins {D1|out_freq|q}]

#**************************************************************
# Set Clock Latency
#**************************************************************

#**************************************************************
# Set Clock Uncertainty
#**************************************************************

set_clock_uncertainty -rise_from [get_clocks {fin}] -rise_to [get_clocks {fin}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {fin}] -rise_to [get_clocks {fin}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {fin}] -fall_to [get_clocks {fin}] -setup 0.170
set_clock_uncertainty -rise_from [get_clocks {fin}] -fall_to [get_clocks {fin}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {fin}] -rise_to [get_clocks {fin}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {fin}] -rise_to [get_clocks {fin}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {fin}] -fall_to [get_clocks {fin}] -setup 0.170
set_clock_uncertainty -fall_from [get_clocks {fin}] -fall_to [get_clocks {fin}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -setup 0.310
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -hold 0.270
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -setup 0.310
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -hold 0.270
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {gate}] -setup 0.360
set_clock_uncertainty -rise_from [get_clocks {clk}] -rise_to [get_clocks {gate}] -hold 0.320
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {gate}] -setup 0.360
set_clock_uncertainty -rise_from [get_clocks {clk}] -fall_to [get_clocks {gate}] -hold 0.320
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -setup 0.310
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {clk}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -setup 0.310
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {clk}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {gate}] -setup 0.360
set_clock_uncertainty -fall_from [get_clocks {clk}] -rise_to [get_clocks {gate}] -hold 0.320
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {gate}] -setup 0.360
set_clock_uncertainty -fall_from [get_clocks {clk}] -fall_to [get_clocks {gate}] -hold 0.320
set_clock_uncertainty -rise_from [get_clocks {altera_tck}] -rise_to [get_clocks {altera_tck}] -setup 0.310
set_clock_uncertainty -rise_from [get_clocks {altera_tck}] -rise_to [get_clocks {altera_tck}] -hold 0.270
set_clock_uncertainty -rise_from [get_clocks {altera_tck}] -fall_to [get_clocks {altera_tck}] -setup 0.310
set_clock_uncertainty -rise_from [get_clocks {altera_tck}] -fall_to [get_clocks {altera_tck}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {altera_tck}] -rise_to [get_clocks {altera_tck}] -setup 0.310
set_clock_uncertainty -fall_from [get_clocks {altera_tck}] -rise_to [get_clocks {altera_tck}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {altera_tck}] -fall_to [get_clocks {altera_tck}] -setup 0.310
set_clock_uncertainty -fall_from [get_clocks {altera_tck}] -fall_to [get_clocks {altera_tck}] -hold 0.270
set_clock_uncertainty -rise_from [get_clocks {gate}] -rise_to [get_clocks {clk}] -setup 0.360
set_clock_uncertainty -rise_from [get_clocks {gate}] -rise_to [get_clocks {clk}] -hold 0.320
set_clock_uncertainty -rise_from [get_clocks {gate}] -fall_to [get_clocks {clk}] -setup 0.360
set_clock_uncertainty -rise_from [get_clocks {gate}] -fall_to [get_clocks {clk}] -hold 0.320
set_clock_uncertainty -rise_from [get_clocks {gate}] -rise_to [get_clocks {gate}] -setup 0.410
set_clock_uncertainty -rise_from [get_clocks {gate}] -rise_to [get_clocks {gate}] -hold 0.380
set_clock_uncertainty -rise_from [get_clocks {gate}] -fall_to [get_clocks {gate}] -setup 0.410
set_clock_uncertainty -rise_from [get_clocks {gate}] -fall_to [get_clocks {gate}] -hold 0.380
set_clock_uncertainty -fall_from [get_clocks {gate}] -rise_to [get_clocks {clk}] -setup 0.360
set_clock_uncertainty -fall_from [get_clocks {gate}] -rise_to [get_clocks {clk}] -hold 0.320
set_clock_uncertainty -fall_from [get_clocks {gate}] -fall_to [get_clocks {clk}] -setup 0.360
set_clock_uncertainty -fall_from [get_clocks {gate}] -fall_to [get_clocks {clk}] -hold 0.320
set_clock_uncertainty -fall_from [get_clocks {gate}] -rise_to [get_clocks {gate}] -setup 0.410
set_clock_uncertainty -fall_from [get_clocks {gate}] -rise_to [get_clocks {gate}] -hold 0.380
set_clock_uncertainty -fall_from [get_clocks {gate}] -fall_to [get_clocks {gate}] -setup 0.410
set_clock_uncertainty -fall_from [get_clocks {gate}] -fall_to [get_clocks {gate}] -hold 0.380

#**************************************************************
# Set Input Delay
#**************************************************************

set_input_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {clk}]
set_input_delay -add_delay -clock [get_clocks {fin}] 0.000 [get_ports {fin}]

#**************************************************************
# Set Output Delay
#**************************************************************

set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[0]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[1]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[2]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[3]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[4]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[5]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[6]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[7]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[8]}]
set_output_delay -add_delay -clock [get_clocks {clk}] 0.000 [get_ports {mem_out[9]}]

#**************************************************************
# Set Clock Groups
#**************************************************************

#**************************************************************
# Set False Path
#**************************************************************

set_false_path -from [get_clocks {fin}] -to [get_clocks {clk}]
set_false_path -from [get_clocks {fin}] -to [get_clocks {gate}]
set_false_path -from [get_clocks {fin_div2}] -to [get_clocks {clk}]
set_false_path -from [get_clocks {fin_div2}] -to [get_clocks {gate}]
set_false_path -from [get_ports {rst_n}] -to [all_registers]
set_false_path -from [get_ports {altera_reserved_tck altera_reserved_tdi altera_reserved_tdo altera_reserved_tms}]

#**************************************************************
# Set Multicycle Path
#**************************************************************

#**************************************************************
# Set Maximum Delay
#**************************************************************

#**************************************************************
# Set Minimum Delay
#**************************************************************

#**************************************************************
# Set Input Transition
#**************************************************************

[sstrell]

You have the output of the synchronizer connected to the rdclk and wrclk inputs of 2 FIFOs.  Is that intentional?  If so, that is considered a clock and needs a create_generated_clock constraint.

[PonPon]

Yes, I want the output of the synchronizer to be rdclk and wrclk of 2 FIFOs.

If I want to do this, how to correctly constraint this signal with create_generate_clock command?

[sstrell]

It depends on out_freq.  You have to specify the properties of this newly generated clock.

create_generated_clock -name <custom name> -source <input to synchronizer> <output of synchronizer>  <output clock relationship to source>

[PonPon]

I’m not really sure about the properties of this clock, can you tell me more information?

out_freq will go into the 2DFF synchronizer, and then the synchronizer output this clock, I only know about this.

[sstrell]

What is the frequency of out_freq?  You have it coming from an outside signal Fin then go though something you've named div2 so there's no way for me to know what the properties of this signal are.

[PonPon]

In my constraint, fin will be a 80kHz signal , so the out_freq which be dived by 2
becomes a 40kHz signal.

[PonPon]

And I do this constraint because I want to measure the FM signal which frequency is between 55kHz~75kHz.

[lishilton]

the same

[ShengN_Intel]

Hi,

May I know does your problem resolved with create_generated_clocks?

If the syncrhonizer Din and Qout clock is the same then you probably not need the clock relationship, constraint like below will do:

create_generated_clock -name <custom name> -source <input to synchronizer> <output of synchronizer>