Adapter for converting Avalon-MM data to Avalon-ST data

[Altera_Forum]

Hi, 

 Does Qsys has any component for converting Avalon-MM data to Avalon-ST data. Or can we build an adapter by using Memory Mapped components in Qsys Interconnect.  Thanks

[Altera_Forum]

The closest thing is a FIFO. You can have one side of the FIFO setup as MM so that you access it with a constant address and the other side is ST. Type 'FIFO' into the library search in Qsys and you'll see all the various FIFOs.

[Altera_Forum]

Hi BadOmen, 

I have a question regarding the Avalon FIFO Memory. I have the input setup as MM, and the output as ST, with packets enabled. Now my question is, are the SOPs and EOPs are generated at for each beat? Say I have the settings as 8 bits per symbol and 4 symbols per beat. Will the SOP be generated on the 1st symbol, and the EOP is generated on the 4th symbol? I was under the impression, I can trigger an SOP and an EOP when I want, i.e. set the SOP bit, send many bytes of data ( definitely more than 4 symbols), set the EOP flag, and send the last byte of data. I could not find a timing diagram in the manual to check how the signalling works. https://www.altera.com/en_us/pdfs/literature/hb/nios2/qts_qii55002.pdf  According to the manual, to set SOP, we have to write to the SOP offset at address 0x1, and then push the data at 0x0. Similarly for EOP, we first write offset 0x1 and then push the data at 0x0. On testing the core in my system, I never seem to be able to trigger on an EOP. The SOP is triggered, but it doesn't have a valid. I am still checking it via signaltap. In the meantime, any more information would be useful in checking if I connected the component wrongly in QSYS.  Thank you, Divya

[Altera_Forum]

I haven't used that FIFO but I think you setup the control register for SOP generation, then write your data, then you disable the SOP generation, keep writing data, then on the last beat you setup the control register to generate EOP, then write your data. So generating SOP or EOP requires control information to be written first so you'll need the control slave to be enabled. Once enabled I would take a look at the user guide for that IP core to see what the register format is to control the FIFO. The user manual should be hyperlinked so that when you click on the documentation button with the FIFO GUI open it should automatically bring you to the IP manual. 

 Also if you set the SOP then send multiple words of data you might end up with multiple SOPs in the stream (probably not what you want).

[Altera_Forum]

Thank you for your reply. In my system EOP was generated, but the signal tap trigger was wrong, so it was never captured.  

 Just a note on the possibility of multiple SOPs: The SOP is sent on the first byte of data following the write to the control register at offset 0x1. Even if the control register SOP bit is not de-asserted, the subsequent bytes of data are sent without an SOP. The flow would be as follows: 1. Set the SOP bit (bit 0) at offset 0x1 (Depending on the master and the addressing, it can also be offset 0x4 in your system). 2. Send data by writing the value at offset 0x00.  3. Before sending the last byte of data, set the EOP bit (bit 1) at offset 0x1 (Depending on the master and the addressing, it can also be offset 0x4 in your system). 4. Send the last byte of data by writing the value at offset 0x00.