Add test bench to project at modelsim

[Altera_Forum]

Hi ,  

i create new project at modelsim and wrote hdl design and there aren't errors . i create test bench file at VHDL and i need to add the file to the project and compile the test bench ,  How do i do it ? thanks .

[Altera_Forum]

If its a modelsim project, you can just add the testbench file to the project like any other VHDL file. 

Or just compile it:  vcom my_testbench.vhd

[Altera_Forum]

You can compile a testbench automatically from Quartus. Add the testbench to your Quartus project. Then go to the menu: 

 Assigments->Settings->Simulation  go to "Compile TestBench" click on TestBench and the add the testbench, etc...  When you compile your project again your testbench will compile too. And you can start Model Sim form Menu:  Tools->Run EDA Tool Simulation Toot->EDA RTL Simulation.  Also, if you do a timing simulation, you can set it to open Model Sim automatically after Compilation.

[Altera_Forum]

Hi ,  

i added the Test Bench to the project and compile the project at Quartos and at Model Sim and it passes successfully without errors . i simulate the Test Bench and look at the waves , the clock and Reset of the Test Bench are shown o.k but the output data of  the project (serial data) is undefined ( shown as U ) .  i investigate the issue and create Test Bench for the lowest component and it works perfect - the serial data shown (attached at file) .  The 2 upper component only instantiate the port to the internal ports of internal component without any design .  what can you recommend me to do more regarding this issue ?

[Altera_Forum]

Post the vhdls and the testbench.

[Altera_Forum]

Hi ,  

i added 4 files :  1.Top file of the Design project - "Top" 2.second block of Design - "Tx" 3.lowest component - "PN_Transmitter"  4.The Test Bench - "testbench"

[Altera_Forum]

* adding the Top file . 

Thanks a lot .

[Altera_Forum]

I found the problem. In the testbench you define the reset signal: 

  signal ResetN : std_logic;  but doesn't have an initial value, so modify it:   signal ResetN : std_logic := '1';  The circuit didn't receive a reset so the ff outputs had an undefined value.  When you simulate you have to stop it manually. You use a assert false directive to stop it when it reaches a special condition.

[Altera_Forum]

Thanks a lot bertulus ,  

i didn't know that i need to give an initial value to Reset , i assumed that it has '1' and after 10 nsec it goes to '0' like i defined it . any way it works great now :) now i'm writing the Receiver Block that supposed to lock on the PRBS data (serial_out) .  Thanks a lot on the support !