Aglix F-tile P&R error

[HongLiang]

we try to put an F-tile  PHY into our design 

there are some error that occurs 

Error (22144): Cannot place the block dp_rx|rx_phy_top_inst|u_dp_gxb_rx|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[1].fgt.rx_ux.x_bb_f_ux_rx at location fgt_q0_ch0_rx because the connected cell dp_rx|rx_phy_top_inst|u_dp_gxb_rx|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[1].rx_ehip.x_bb_f_ehip_rx|bb_f_ehip_rx_xcvr25g0 can only be placed in location(s) bb_f_ehip_rx_xcvr25g[1], bb_f_ehip_rx_xcvr25g[5], bb_f_ehip_rx_xcvr25g[9], bb_f_ehip_rx_xcvr25g[13], bb_f_ehip_rx_xcvr25g[17], bb_f_ehip_rx_xcvr25g[21].

Error (22658): Cannot place block dp_rx|rx_phy_top_inst|u_dp_gxb_rx|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[1].fgt.rx_ux.x_bb_f_ux_rx in location fgt_q0_ch0_rx because it makes the block dp_rx|rx_phy_top_inst|u_dp_gxb_rx|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[2].fgt.rx_ux.x_bb_f_ux_rx unplaceable

Error (22658): Cannot place block dp_rx|rx_phy_top_inst|u_dp_gxb_rx|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[1].fgt.rx_ux.x_bb_f_ux_rx in location fgt_q0_ch0_rx because it makes the block dp_rx|rx_phy_top_inst|u_dp_gxb_rx|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[3].fgt.rx_ux.x_bb_f_ux_rx unplaceable

Error (22144): Cannot place the block dp_rx|rx_phy_top_inst|u_dp_gxb_rx|directphy_f_0|dphy_hip_inst|persystem[0].perxcvr[1].fgt.rx_ux.x_bb_f_ux_rx at location fgt_q0_ch1_rx because the connected cell dp_rx|rx_phy_top_inst|u_dp_gxb_rx|directphy_f_0|dphy_hip_inst|persystem[0].perehip_rx[1].rx_ehip.x_bb_f_ehip_rx|bb_f_ehip_rx_xcvr25g0 can only be placed in location(s) bb_f_ehip_rx_xcvr25g[1], bb_f_ehip_rx_xcvr25g[5], bb_f_ehip_rx_xcvr25g[9], bb_f_ehip_rx_xcvr25g[13], bb_f_ehip_rx_xcvr25g[17], bb_f_ehip_rx_xcvr25g[21].

 what are the problems?

is possible for the pin allocation to conflict?

I just keep the pin assignment free run by Quartus and not specify the pin allocate.

[Ash_R_Intel]

Hi,

There are some rules to be followed for the F-tile. Please check following link: https://www.intel.com/content/www/us/en/docs/programmable/683872/22-3-4-2-0/f-tile-placement-rules.html

There are tools available for you to easily understand channel assignment as per your requirement. See following page: https://www.intel.com/content/www/us/en/docs/programmable/683872/22-3-4-2-0/supported-tools.html

Hope this helps. In case you still need help, please provide us with your design requirement along with the .ip file of the F-tile IP that you used.

Regards

[Ash_R_Intel]

Hi,

Any update on this case? Is your issue resolved?

Regards

[Ash_R_Intel]

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

[jmcguire3]

Bump.  F-tiles appear to have bus-twist issues in Quartus.  More info here:

https://community.intel.com/t5/Programmable-Devices/Agilex-F-Tile-bus-reversal-twist/m-p/1559892#M94136

[binupr]

I am getting similar errors for AGF027 board. Is this due to bus-twist? Is this a Quartus issue and will it get fixed? I am using Quartus 23.4.