I'm looking for a similar process to something I can do with Xilinx in Quartus. In Vivado a tcl command 'write_csv' can generate a CSV output file with the part pins, bank, site type, and pin alias all populated for the given project part.
I understand that pinout files are available from https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html, but these do not have a consistent structure in column defining from part to part that makes parsing unnecessarily challenging.
Is there anything I can use to generate an output file that at least maps the pin, bank, and pin name/function given an empty project with a defined part?
Sorry, I dont think so without top module in quartus we can export the pin assignment. Kindly let me know how i can help further.
Thank you ,