The design runs off a 250 Mhz clock with a 125 Mhz clock enable. I added the set_multicycle_path constraint to the .SDC file and the design does meet timing. I'm a little concerned how the tool implements the clock enable at the register level. I'm seeing some run-time issues with the design and they appear to be associated with the 125 Mhz clock enable logic. Looking at the RTL Viewer, a clock enable is implemented as a dual mux. The schematic should work, but I'm concerned about timing.
Code... data_in : process (clk_250) begin if clk_250= '1' and clk_250'event then if reset = '1' then lut_data_in <= (others => '0'); elsif clk_125_ce = '1' then lut_data_in <= lut_data_i_reg; end if; end if; end process; RTL Viewer... https://www.alteraforum.com/forum/attachment.php?attachmentid=9274 Any suggestions? I tried using the direct_enable with no success and I'm not sure if I should be concerned about this, or looking in a different section of the design for the error. Code.. attribute direct_enable: boolean; attribute direct_enable of clk_125_ce: signal is true; Thanks
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I suspect thats not the exact code that created the RTL diagram, as we're looking at the code for the lut_data_in register, and you have the RTL diagram for lut_data_i_reg.
For reference, altera registers have no sync reset port, so sync resets have to be emulated with a mux - that is what you are seeing with this diagram, but for the lut_data_i_reg register, not the one in the code.Sorry... Copied the wrong code.
data_in_iob : process (clk_dac) begin if clk_dac = '1' and clk_dac'event then if reset = '1' then lut_data_i_reg <= (others => '0'); elsif clk_125_ce = '0' then lut_data_i_reg <= lut_data_in; end if; end if; end process; The same issue popsup for all code using the 125 clock enable. It could be a postive or negative chip enable. I looked at Altera's set_multicycle_path design example and their design shows the correct implemntation in the RTL veiwer. https://www.alteraforum.com/forum/attachment.php?attachmentid=9275
You can try these two variants:
with a synchronous resetdata_in : process(clk_250)
begin
if rising_edge(clk_250) then
if (reset = '1') or (clk_125_ce = '1') then
if reset = '1' then
lut_data_in <= (others => '0');
else
lut_data_in <= lut_data_i_reg;
end if;
end if;
end if;
end process;
with an asynchronous reset data_in : process(clk_250, reset)
begin
if reset = '1' then
lut_data_in <= (others => '0');
elsif rising_edge(clk_250) then
if (clk_125_ce = '1') then
lut_data_in <= lut_data_i_reg;
end if;
end if;
end process;
The clk_125_ce is generated by a register.
--125 MHz generated clock from 250 MHz enable_reg : process (clk_250, reset) begin if reset = '1' then clk_125_i <= '0'; elsif clk_250 = '1' and clk_250'event then clk_125_i <= not clk_125_i; end if; end process; clk_125_ce <= clk_125_i;--- Quote Start --- It could be your device does not have clk enable port on its registers --- Quote End --- Changed the Altera's set_multicycle_path design to be the same device as my project (Arria II GX) and I get the same results. The clk enable port appears at the register. Any other suggestions? Thanks
Fixed the mux issue.
It appears that the natural priority that matches the core register hardware, should be followed to avoid the mux scheme. 1. Asynchronous Clear, aclr—highest priority 2. Asynchronous Load, aload 3. Enable, ena 4. Synchronous Clear, sclr 5. Synchronous Load, sload 6. Data In, data—lowest priority Thanks,