Clock constraints specified in sdc file reset by compilation process

[sth125]

Hello,

I am using Quartus Prime Lite Edition to compile logic for a MAX V 5M1270ZT144C4 CPLD.

I created an sdc file that contained a constraint for only 1 clock, i.e.

create_clock -name {CLK1} -period 20.000 -waveform { 0.000 10.00 } [get_ports { CLK1 }]

I actually used an sdc file from another project (with the exception of the file name).  That project has most of the same logic.

The Timing Analyzer showing timing errors and Clocks are shown in the image below. 

Why did compilation process change the CLK1 constraint?

Also, why were the other Clock constraint created.  

The project was created from another project that had the same code (i.e.. FreqDivBy16, 5us_Filter and ect) and that project didn't change or generate new clock constraints.

[sth125 · Accepted solution]

I solved the issue.

I just needed to add the sdc file in my project.  I had thought it would automatically include it.

[sstrell]

As you discovered, if no clock constraints are found, all clocks default to 1 GHz, which is basically useless.  Glad you figured out the issue.