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Please advise me how to get rid of error from the title. It appears when I try to compile following code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ff IS
PORT(
t : IN std_logic;
s : IN std_logic;
r : IN std_logic;
q : OUT std_logic;
qi : OUT std_logic);
END ff;
ARCHITECTURE behavior OF ff IS
SIGNAL qs : std_logic;
BEGIN
PROCESS(r,s,t)
BEGIN
IF (r='0') THEN
qs<='0';
ELSE
IF (s='0') THEN
qs<='1';
ELSE
IF (rising_edge(t)) THEN
qs<=not(qs);
END IF;
END IF;
END IF;
END PROCESS;
q <= qs;
qi <= not(qs);
END behavior;
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Are you instantiating this block on its own or part of a larger system?
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--- Quote Start --- Are you instantiating this block on its own or part of a larger system? --- Quote End --- on its own
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Have you tried with elsif rather than if? What chip are you targeting?
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