Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16594 Discussions

Compile Error / EPCS multiple pin problem in DE2-35

Dolemy
Novice
1,170 Views

Hello, I am having trouble using EPCS16. Generating on NIOS II works well

but I get this error when I try to do a full compile in Quartus

 

 

 

"Error (176310): Can't place multiple pins assigned to pin location Pin_E3 (IOC_X0_Y34_N0) Info (176311): Pin ASDO is assigned to pin location Pin_E3 (IOC_X0_Y34_N0) Info (176311): Pin ASDO is assigned to pin location Pin_E3 (IOC_X0_Y34_N0)."

 

 

I heard that this problem can be solved by setting Device-dual purpose pin-User as regular I/O, but even after changing the setting, I still get the same problem. I am attaching my error message and Verilog HDL file for reference.

 

 

I am using Quartus II 13.0spi / DE2_35 board.

My pin assignments are as follows, and I did it according to the DE2-35 manual. The DE2-35 Pin Assignment did not have pin numbers, but I found them in the circuit diagram, so I referred to that.

PIN_E3 -to ASDO

PIN_D3 -to NCSO

PIN_N6 -to DCLK

PIN_N3 -to DATA0

 

by the way, I changed the file extensions for some files to upload them. By removing the "txt" at the end, you should be able to use them.

Thank you for reading this.

 

multiple pins error.png

dual.png

serial_configuration.png

  

0 Kudos
11 Replies
NurAiman_M_Intel
Employee
1,144 Views

Hi,


Do you only make changes to ASDO pin (use as regular IO), or do you also make changes to nCEO pin? Can you only change the ASDO pin in as regular IO?


Regards,

Aiman


Dolemy
Novice
1,138 Views

Thank you for your response.

I only made changes to the nCEO option in the "dual-purpose pins" setting.

There were no changes made to ASDO and nCSO.

Additionally, for the ASDO pin that you asked about, it can be changed to either a regular I/O or a programming pin.

 

If you have any information you would like to know, please let me know.

I will respond immediately upon seeing it.

0 Kudos
NurAiman_M_Intel
Employee
1,133 Views

Hi,


The error mention Pin ASDO;


Error (176310): Can't place multiple pins assigned to pin location Pin_E3 (IOC_X0_Y34_N0) Info (176311): Pin ASDO is assigned to pin location Pin_E3 (IOC_X0_Y34_N0) Info (176311): Pin ASDO is assigned to pin location Pin_E3 (IOC_X0_Y34_N0)."


Hence, I suspect the ASDO pin was the cause of the error. Can you only change ASDO pin to "regular IO"?. Do not make changes to nCEO pin. Keep the nCEO pin just as it is from the start. Then try again. Still the same error?


Regards,

Aiman


Dolemy
Novice
1,127 Views

Thank you. I only mentioned ASDO in my previous message, but in fact, nCSO also has the same issue. In the first image, two errors are reported. I will provide information on both of these errors:

Error (176310): Can't place multiple pins assigned to pin location Pin_E3 (IOC_X0_Y34_N0) Info (176311): Pin ASDO is assigned to pin location Pin_E3 (IOC_X0_Y34_N0) Info (176311): Pin ~ASDO~ is assigned to pin location Pin_E3 (IOC_X0_Y34_N0)

Error (176310): Can't place multiple pins assigned to pin location Pin_D3 (IOC_X0_Y34_N1) Info (176311): Pin nCSO is assigned to pin location Pin_D3 (IOC_X0_Y34_N1) Info (176311): Pin ~nCSO~ is assigned to pin location Pin_D3 (IOC_X0_Y34_N1)

Regarding your previous response, I can change the ASDO pin to AS input tri-stated. However, even if I compile it in its original state, the same issue still occurs.

0 Kudos
FvM
Valued Contributor III
1,086 Views

Hello,
looks like you have a second module besides nios2e that's connecting to AS memory. ASDO is the top level pin you have defined ~ASDO~ is something different. Specifying dual purpose pins as regular IO is basically correct when using user declared AS pins.

You can e.g. disconnect the nios AS pins by outcommenting the top level pins and check the compilation report to see what's connecting else. Can it be that nios is configured for internal AS memory connection and you are using the external pins erroneously?

 

Regards

Frank 

Dolemy
Novice
1,058 Views

Dear Frank,

Thank you for your response. I understood that "outcommenting the top level pins" means releasing the pins declared for EPCS16. If I understood correctly, I released the 4 pins declared for EPCS16 and compiled without any error messages.

 

The problematic pins are E3 connected to ASDO and D3 connected to nCSO. If only these two pins are reassigned and the code is recompiled, the same issue occurred.

 

Could not checking the "Automatically select dedicated active serial interface, if supported" option in the configuration when adding the EPCS controller to Qsys be the cause of the issue?

 

Regards,

Sung zun

0 Kudos
Dolemy
Novice
1,058 Views

EPCS16_SCHEMATIC.pngThis image is the schematic for the EPCS on the DE2-35 board.

0 Kudos
Dolemy
Novice
1,051 Views
0 Kudos
NurAiman_M_Intel
Employee
981 Views

Hi,


Before doing the compilation, did you try to do the pin assignment by yourself? Per my checking, you just need to leave the pin as it is.


Also, have you try to compile with the latest quartus version?


Regards,

Aiman


0 Kudos
NurAiman_M_Intel
Employee
944 Views

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


0 Kudos
Dolemy
Novice
880 Views

I’m sorry for the late reply. Actually, I couldn’t solve that problem, but I succeeded in using EPCS. I left it to automatically assign pins without manually assigning them, so I was able to use EPCS and succeeded in programming my code into FPGA. So I don’t think I can answer any more about that.

0 Kudos
Reply