Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
17267 Discussions

Compile error whilel using Quartus Prime

Altera_Forum
Honored Contributor II
8,654 Views

I am getting the following compile errors while compiling a project in quartus prime, as follows: 

Error (275029): Incorrect connector style at port "dataa[7..0]" for symbol "inst" of type mult 

 

Error (275029): Incorrect connector style at port "datab[7..0]" for symbol "inst" of type mult 

 

 

 

Error (12153): Can't elaborate top-level user hierarchy 

 

https://alteraforum.com/forum/attachment.php?attachmentid=15391&stc=1 I tried changing to bus line, but it dint work. I also tried using a diagonal bus tool while drawing. That dint work either. 

 

Please help.
0 Kudos
7 Replies
Altera_Forum
Honored Contributor II
6,003 Views

You've got a single bit wire connecting from the datab input to what looks like the clock input on the ram instance. There's also a wire shorting between the clock and dataa inputs of mult. 

 

They're on the left edge of the mult instance so they are hard to see.
0 Kudos
Altera_Forum
Honored Contributor II
6,003 Views

Thanks sstrell. I will try it out and see.

0 Kudos
Altera_Forum
Honored Contributor II
6,002 Views

Hi, I corrected the design entry. I am finally seeing the following errors, which I have been unable to get rid of: 

1. Incorrect connector style at port "dtaa[7..0]" for symbol "inst" of type mult 

2. Can't elaborate top-level user hierarchy 

Please help.:(. Modified schematic attached.
0 Kudos
Altera_Forum
Honored Contributor II
6,002 Views

Hi, 

 

You can take a look at the attached project, I've created a almost identical design setup and have got it to compile successfully. The device used is different , while the LPM blocks used are almost the same with minor variations. You can use this as a reference.
0 Kudos
Altera_Forum
Honored Contributor II
6,002 Views

You still have multiple shorts. Delete all the wires until you don't see any crosses or rounds and reconnect everything.

0 Kudos
Altera_Forum
Honored Contributor II
6,002 Views

 

--- Quote Start ---  

You still have multiple shorts. Delete all the wires until you don't see any crosses or rounds and reconnect everything. 

--- Quote End ---  

 

 

Thank you Daixiewen. I tried doing that but a round still appears. I used a diagonal bus line to go from the first data(0..7) of mult to input vcc by clicking on one end and dragging till it meets the other end. A dot then appears. How do I get rid of it or draw so that it doesnt appear? Thanks in advance!
0 Kudos
Altera_Forum
Honored Contributor II
6,002 Views

Delete and re-add components or drag components away from the shorts and delete them. Or drag a selection around the shorts to highlight them and delete.

0 Kudos
Reply