Re: Compile freezing when used indexing signal with an array is greater than 15000

Altera_Forum · ‎01-15-2010

Hi,

I'm facing a strange issue with Quartus II.

ModelSim simulations showed that the software is running well and it has no issues. However, when using Quartus to compile, it simply the compilation freezes on 2%.

On top of the architeture, the image_array type is defined through of

subtype    elements    is    std_logic_vector(7 downto 0); 
type    image_array    is    array(0 to 307199)    of    elements;

The i_std signal (internal) is being used to store a image (through a linear array)

constant    i_std        : image_array    :=    (x"AA", x"1B", x"10", x"10", x"10", x"10",...,x"B0", x"B0", x"10",x"10");

A internal signal (counter) is defined in order to index the array defined by i_std:

signal counter_c : integer range 0 to 307200 := 0;

In the body of the architeture, we have a process that on falling edge of a clock signal, it increases the counter (counter_c) and it

assign to an out signal of the entity the values of i_std sequentially through the index increasing:

indexprocess: process(CLK)
begin
    
    if (falling_edge(CLK)) then
        if (counter_c < 307200) then
            VIDEO_DATA <= i_std(counter_c);
            counter_c <= counter_c + 1;
        end if;
    end if;
CLK and VIDEO_DATA are defined as in and out ports respectively.
end process indexprocess;

As I said, it works perfectly on ModelSIM, however, it stop at 2% of compilation on quartus.

The problem doesn't happen if I replace at the process the counter_c index to a constant value.

If the counter_c is defined with a size smaller than 15000, the compilation finishes sucessfully.

I also tried to exchange the FPGA on quartus to a most powerful one (with more memory, etc), but the problem continues to happen.

Have any one already had a similar problem ?

I thank you your help in advance !

BR,

Rosseto

Altera_Forum · ‎01-15-2010

In my test, Quartus (V9.0) had no problem to infer a 512k x 8 ROM from similar code. I simply used the Quartus single port ROM template and changed the address width to 19.

It could be that the problem is with your initialization method? You may want to try with a *.hex file and an explicite altsynram MegaFunction instance.

Altera_Forum · ‎01-16-2010

Hi FVM,

Thank you for your answer !

I've downloaded the last version of Quartus II (9.1) and the problem is still happening with this version.

I've uploaded the vhd file into rapidshare website, follow the link below

rapidshare.com/files/

336384256/Test.vhd.html

(please join the parts.. I still haven't permission to post links..)

I started a new project, and I've set the FPGA with the following model

EP3C120F780I7 (Cyclone III family)

As a alternative I'll try to follow your hints, but I really 'd like to know the cause of the problem that I faced..

Best Regards,

Altera_Forum · ‎01-18-2010

Considering my previous test, it seems to me that the huge constant initializer rather than the array size causes the problem. If you actually

need this kind of VHDL text for your projects, file a support request to Altera.