Constraining timing on configurable PLL output for a range of frequencies

[Altera_Forum]

Hi  

 I am using re-configuration feature in Altera FPGAs PLLs, so I am generating a highest frequency of 300 MHz and a lowest frequency of 25 MHz and bunch of frequencies in between on the fly.  I am wondering about how to constrain the piece of design that runs on PLL output so that I have reliable operation within the max and min frequency range.  Previously I only constrained for the max case i.e. 300 MHz assuming that if this design is able to run at max then should be fine at min as well. However, I recently came across some information indicating that my assumption might not be true and I may need to constrain for the lower limit as well. Now I don't fully understand how the lower limit of frequency will play  a role in possible malfunctioning of the design (it likely has to do with combinational delays) and don't know if the information I came across is true or applicable in my case or not.  This piece of logic running off from PLL output is standalone and doesn't have any dependence interfaces that might cause problems with it running slow or fast.  Google search isn't returning much, so just wondering if there's a way to constrain a design for max and min frequency output from PLL in sdc commands ?   Thanks

[Altera_Forum]

If the logic in your design operates at 300MHz then it will work at 25MHz as well. There's no reason, indeed no way, to constrain it for a lower limit at well. 

 However, the PLLs are a different issue. These do have a minimum frequency at which they will operate. You also need to ensure that the parameters you set when configuring the PLL combined with the source frequency you're giving it don't end up trying to operate the PLL outside its limits.  Are you setting up the PLL for one frequency and then driving it with another? This is, potentially, going to cause issues.  Cheers, Alex

[Altera_Forum]

Hi a_x_h_75 

 Thanks for your reply. Yes, the PLL does operate in the valid operating range for both input and output.  The input frequency (ref clk) to the PLL doesn't change. However, I am re-configuring the Output frequency from the PLL by changing the clock multiplier and divider values in the PLL (M, N, C values).  So input frequency is fixed at 100 MHz but the output frequency can change to either 300 MHz or 25 MHz or some other frequencies in between.   MS

[Altera_Forum]

What is this information you've come across that suggests you need to constrain for a lower limit? Excessive combinatorial delays only compromise a maximum working frequency - unless you have combinatorial feedback which, unless very carefully considered, I'd consider very bad practice. 

 If you're seeing bad behaviour when operating at your lower frequency only then I think you need to be a little more specific with what you're seeing.  Cheers, Alex