Constraints on DDR signals

[Yamada1]

It would be helpful if you could teach me how to give constraints to the DDR signal from the ADC.

The conditions are as follows.

　CLK　: 200MHz

　DATA resolution: 14bit

　Signal level: LVDS

　CLK-DATA skew:

　　　min　1ns

　　　max　1.6ns

(Rise/fall of CLK at the center of DATA)

The source synchronous system is used, and the clock and data are directly connected to the FPGA.

Also, data and clock are wired with equal length on the board.

In the case of DDR, I am aware that constraints are set for both rising and falling edges, so the constraints are described as follows.

--From here

create_clock -name DCLK -period 5 [get_ports {CLK}]

set_input_delay -clock { CLK } -max 1.5 [get_ports {DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[ 9] DATA[10] DATA[11] DATA[12] DATA[13]}]

set_input_delay -clock { CLK } -clock_fall -max -add_delay 1.5 [get_ports {DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[ 8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13]}]

set_input_delay -clock { CLK } -min 0.9 [get_ports {DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[ 9] DATA[10] DATA[11] DATA[12] DATA[13]}]

set_input_delay -clock { CLK } -clock_fall -add_delay 0.9 [get_ports {DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13]}]

--to this point

It seems that the data is being received normally, but the timing analysis did not satisfy the setup slack of DATA[0] to DATA[4].

In addition, I posted it once, but it was not reflected, so I posted it again with the same content.

Please pardon any duplication.

Sorry for the inconvenience, but thank you in advance.

that's all

[AdzimZM_Intel]

Hi Sir,

Thank you for submitting your question in Intel Community.

I may need more information regarding to this issue.

Can you provide the timing analysis report here? Or can you share a design that can replicate the issue?

Also, can you provide the EMIF IP setting together with memory datasheet that you used to configure the EMIF IP?

Regards,

Adzim

[Yamada1]

Thank you for your response.

We are very sorry, but please refrain from providing reports.

Therefore, it would be helpful if you could teach us how to describe the constraints when performing DDR constraints instead of the numerical values listed.

We apologize for the inconvenience, but thank you.

that's all

[Yamada1]

The other day, I stated that it would be difficult to provide the report, but I have received internal approval, so I am attaching the report file.

I couldn't attach it if it was .rep, so I made it .txt.

In addition, the signal names CLK and DATA in the question are ADC_CLK and ADC_DATA on the report file.

It would be helpful if you could teach me something.

[AdzimZM_Intel]

Hi,

May I know which IP that you used in the design?

Can I get the timing report for the failing path?

Can you export from the timing analyzer?

Regards,

Adzim