Create an IP like the Qsys Clock Source

[DWang108]

1 why ClockSourceIP can export clk & reset automatic

2 why NOT ClockSourceIP connect clock signal itself

but ClockBridgeIP try to connect clk loop to itself

3 I want to create an IP which behave like the ClockSource

may I have some tcl sample to do that

thx

David Wang

xinqiang_wang@yahoo.com

[RichardTanSY_Altera]

Clock Source is a clock output interface that drives a clock signal out of a component. Clock output interfaces cannot have reset signals.

Its clock input interfaces provide synchronization control for a component. A typical component has a clock input to provide a timing reference for other interfaces and internal logic.

Reference:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-platform-designer.pdf#page=161

Clock bridge allows you to route between Qsys subsystems. The Clock Bridge connects a clock source to multiple clock input interfaces. You can use the clock bridge to connect a clock source that is outside the Platform Designer system. Create the connection through an exported interface, and then connect to multiple clock input interfaces.

Reference:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-platform-designer.pdf#page=212

You can refer to the Quartus scripting manual regarding clock source tcl scripting information.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/tclscriptrefmnl.pdf