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Custom type simulation

Altera_Forum
Honored Contributor II
‎05-17-2018 11:30 AM
1,550 Views

Hi, 

in my VHDL design I have custom type: 

 

type T_STATE is (STOPPED, STARTED, RUNNING); 

signal state: T_STATE; 

 

In Simulation Waveform editor I want to see value of state signal so I go to Insert Node or Bus and I add state signal so it appears in the left column of Simulation Waveform Editor. I run simulation, however the value of state signal is always u (undefined probably). I'm sure state has always some value (STOPPED or STARTED or RUNNING). Can you please help how to display value of custom type in Simulation waveform editor?
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Altera_Forum
Honored Contributor II
‎05-17-2018 12:57 PM
362 Views

If you use the Quartus simulator, it simulates the netlist, so it will not use your custom type. You will need to use an RTL simulator, like modelsim, to be able to see your custom type.

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Altera_Forum
Honored Contributor II
‎05-17-2018 01:25 PM
362 Views

Thank you!

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