I'm trying to implement a X16 DDR3 EMIF in a single bank (2K) of a Cyclone 10GX220. Quartus gives me an error saying that it won't fit. There are enough pins in the bank if I omit the DM signals. I'm letting Quartus assign the pins, although I've tried manually assigning them and get the same result. If I implement a X8 EMIF I get no complaints from Quartus. Is this really a limitation of the Cyclone 10GX, it requires at least two banks at 1.5V to implement a X16 EMIF?
IIRC, each bank is only 48 pins and 3 of the 4 I/O lanes (12 pins each) must be used for address/command. That means you can only fit a x8 EMIF in a single bank (DQ + DQS pins in the 4th lane leaving 3 unused pins). You would need 2 banks for x16.
This is a huge limitation. I have to assign an entire 2nd bank as 1.5V in order to use just a few pins. 1.5V is not very standard for anything but DDR memory. This leaves that bank fairly useless without external level translators.
I'm beginning to regret my decision to use the Cyclone 10GX.
Unused I/O lanes in a bank can be used for GPIO. You're not losing the other 36 pins. EDIT: oh your concern is the voltage. You don't have any other I/O you need at 1.5.
As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
