Schematic drawing tool (also used in Intel Quartus Prime

[TRaym1]

The Intel Prime software does support the older .GDF schematic files where you can draw logic, wiring, input and output pins, well you choose what component library you wish to use.

I have drawn all the gates with my design with the drawing but is it even possible to compile all gates drawn with the schematic editor?  It also seems that the gates need to be organized logically is that correct?  So how could I choose *All gates used in design* organize them the way I need to, then how do I choose or even start the compiling process, mine is all greyed out and I cannot select anything.  

Also I was under the impression that the Intel Quartus Prime is FREE so how does that work with the licensing, is that free but will it still let me:  Compile, Run Synthesis,  Run Benchmark?

I said that because it occurred to me, is that why the compile window is greyed out because of something to do with the so called FREE whatever I do not understand how that is supposed to be setup in Quartus Prime FREE version (So called anyway so far), Sorry Im always battling the stupid license its a royal pain I was told the FREE version you dont need a license, is that true?

Yeah Yeah I know about the stupid verilog code thing but right now the GDF editor is still included in the dang software and THAT is what I understand, mainly with the latter CMOS, not the older TTL CMOS though.  I should say the CMOS gates.

Also in FPGA or even the GDF editor, pertaining to Flip flops can that still be drawn as just the square and everything used in Flip flops?  I seem to remember reading that FPGA may not like the square representation and may cause an error, is that the case?  So would I have to draw the Flip flip with the CMOS gates instead of the squares?  The older Quartus II 6.1 software library for Flip flops just draws the flip flops as a square, I havent had a chance to see if that is the same in the Quartus Prime software, Yet.  I cannot remember what I read that in but I took that to mean during the compiling process that would cause an error? 

[sstrell]

A lot going on here.

First, I think you mean .bdf, not GDF.  That's a schematic design file.

Second, if you are using Quartus Pro, you can no longer create a schematic design.  Schematic design is still supported in Lite and Standard.

Speaking of which, Lite is the free version of Quartus.  You don't indicate what you've downloaded or installed, but if you need the free version, it's Lite.  It supports the whole process of design, compilation, and device programming for the devices it supports.

If you have a .bdf and it's set as your top-level design file, you can just compile the project.  I'm not sure what you are referring to about organizing the gates.  Just run a full compilation.

As for adding flip-flops or any other basic logic to a schematic, just double-click in any blank space in the schematic and choose a flip-flop (D or otherwise) from the symbol library.  I'm not sure what you're talking about regarding drawing shapes.

[ShengN_Intel]

Hi,

This related video https://www.youtube.com/watch?v=bzolOHfyZ4w probably can help you out.

This video https://www.youtube.com/watch?v=saOe5tBEJzE explains how to convert .bdf to verilog/VHDL file.

This video https://www.youtube.com/watch?v=QZ_j0KVURg4 explains how to convert verilog/VHDL file to .bsf and to be used in .bdf

Thanks,

Regards,

Sheng