Design facing fitter congestion need help

[pavanhegde]

Hello Intel community,

Device used : 10AX057K4F35I3SG Family: Arria 10

I am facing the following and any help highly appreciated.
I have a huge design and I am getting routing congestion warning when build is completed

This is fitter report
Fitter Resource Usage Summary ;
------------------------------------------------------------+-------------------------+-------+
Resource ; Usage ; % ;
------------------------------------------------------------+-------------------------+-------+
Logic utilization (ALMs needed / total ALMs on device) ; 139,919 / 217,080 ; 64 % ;
ALMs needed [=A-B+C] ; 139,919 ; ;
[A] ALMs used in final placement [=a+b+c+d] ; 176,349 / 217,080 ; 81 % ;
[a] ALMs used for LUT logic and registers ; 57,016 ; ;
[b] ALMs used for LUT logic ; 44,742 ; ;
[c] ALMs used for registers ; 74,031 ; ;
[d] ALMs used for memory (up to half of total ALMs) ; 560 ; ;
[B] Estimate of ALMs recoverable by dense packing ; 37,808 / 217,080 ; 17 % ;
[C] Estimate of ALMs unavailable [=a+b+c+d] ; 1,378 / 217,080 ; < 1 % ;
[a] Due to location constrained logic ; 0 ; ;
[b] Due to LAB-wide signal conflicts ; 171 ; ;
[c] Due to LAB input limits ; 1,207 ; ;
[d] Due to virtual I/Os ; 0 ; ;
; ; ;
Difficulty packing design ; Low ; ;
; ; ;
Total LABs: partially or completely used ; 21,708 / 21,708 ; 100 % ;
-- Logic LABs ; 21,652 ; ;
-- Memory LABs (up to half of total LABs) ; 56 ; ;
; ; ;
Combinational ALUT usage for logic ; 177,275 ; ;
-- 7 input functions ; 677 ; ;
-- 6 input functions ; 35,960 ; ;
-- 5 input functions ; 18,012 ; ;
-- 4 input functions ; 15,260 ; ;
-- <=3 input functions ; 107,366 ; ;
Memory ALUT usage ; 1,008 ; ;
-- 64-address deep ; 0 ; ;
-- 32-address deep ; 1,008 ; ;
; ; ;
; ; ;
Dedicated logic registers ; 325,662 ; ;
-- By type: ; ; ;
-- Primary logic registers ; 262,093 / 434,160 ; 60 % ;
-- Secondary logic registers ; 63,569 / 434,160 ; 15 % ;
-- By function: ; ; ;
-- Design implementation registers ; 318,507 ; ;
-- Routing optimization registers ; 7,155 ; ;

Please guide me if there are any optimization technique in the tool. 
The design is almost optimised and very slim possibility of reducing the resources.

Thank you
Regards
Pavan Hegde

[Nurina]

Hi Pavan,

Can you provide your qar file so I can further investigate the problem? To do this, go to Project->Archive Project...

Thanks

Nurina

[pavanhegde]

Hello @Nurina 

I deeply sorry I cannot share the project as it is confidential

Thank you
regards
Pavan Hegde

[Nurina]

Pavan,

Can you also let me know which version of Quartus and what OS you are using?

Thanks

Nurina

[pavanhegde]

Hello @Nurina 

Thanks for the quick reply.

I am using Quartus 18.1
OS : Cent OS 7

Thank you
regards
Pavan Hegde

[Nurina]

Hi Pavan,

Are you able to share your project privately through e-mail? I will send you an e-mail and you can e-mail me your project if you like.

Regards,

Nurina

[Nurina]

Hi Pavan,

The congestion might be caused by the place and route, this problem arises a lot in Arria 10 devices. Maybe you can set a LogicLock region to solve this.

You can refer to this document on Design Optimization Floorplan: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-design-optimization.pdf#page=121

Regards,

Nurina

[pavanhegde]

Hello @Nurina 

I am new to Intel design flow and LogicLock region technique is little difficult for me

However I tried different method.

I changed few settings in Analysis and synthesis , fitter settings.

Earlier option:-1 Unlimited     

New option: 21708 (Maximum Number of LABs)

Earlier option : balanced

New option: Area (Optmization technique)

Earlier option: 1.0

New Option: 2.0 (Placement Effort Multiplier)

The utilization of LABs is 99% now ( almost 300 LABs reduced)

Do you know what is crtical limit for the usage of LABs?

Please suggest me

Thank you
Regards
Pavan 

[Nurina]

Hi Pavan,

Critical limit would be 100%. As long as it's less than that it should be fine.

Can your design achieve a successful fit now?

Regards,

Nurina

[Nurina]

Hi Pavan,

We did not receive any response to the previous question/reply/answer provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,
Nurina

PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.

[pavanhegde]

Hello  @Nurina 

Sorry for the delay.
Yes the LAB usage was reduced to 97% and we have reduced ALM  (optmised the code)

But the results of the FPGA build are not consistent

Sometimes the build will take 100% 
Strange  thing is it is not showing any routing congestion even LAB's utilization is 100%

I know that 100% LAB is not good but since there is no warning or error it is confusing

How about your opinion?

Thank you
Regards
Pavan Hegde

[Nurina]

Hi Pavan,

In my opinion it's best to use up around 80-90% resources so you can use the free resources for debugging like SignalTap. If you don't plan on using SignalTap then I think 97% is fine.

With regards to the inconsistent resource usage, this is expected because you didn't set logic lock region, so the fitter will place & route your design differently at each compilation, using different amount of LAB.

Regards,

Nurina

[Nurina]

Hi Pavan,

We did not receive any response to the previous question/reply/answer, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,
Nurina

PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.