Yes, If I disable logic lock regions . Fitter will pass without giving errors.
But , frequency achieved will drop drastically.
I want to retain maximum frequency which I had achieved while creating logic lock region .I have explained the same below:-
Say I have 3 modules:
1) Top module
2) sub-module A-(achieved freq 150Mhz when compiled separately)
3) sub-module B-(achieved freq 200 Mhz when compiled separately)
After I instantiate sub-modules A and B in top module , I am getting 80Mhz and 110 Mhz from both respectively.
So , I thought if I retain the same fitter placement of module B (applying logic lock and design partitioning) I can get same frequency i.e, around 200 Mhz on the Top module .
Please Note that: Fitter used to behave unusally while merging 624 9x9 multipliers into 208 DSPs (cyclone V device) and used to fail sometimes. So Design partiton/ logic lock is very important for me .
But here ,if I try to retain the routing and placement netlist , I get the above error .
If I remove logic lock fitter will pass but timing falls drastically.
So, please suggest me how to solve this issue.
